AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 95

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.4.5
9.2.4.6
9.2.4.7
9.2.4.8
32002F–03/2010
Trapping opcode 0x0000
Single stepping
Event on EVTI pin
Abort command
In Flash-based microcontrollers, the opcode 0x0000 can overwrite any other opcode without
having to erase and reprogram the Flash. Therefore this instruction can enter Debug Mode, as
for the breakpoint instruction. However, the opcode 0x0000 is also a valid part of the instruction
set (ADD R0,R0 in AVR32) and can be part of the software to be debugged. Therefore, the user
must write the DC:TOZ (Trap Opcode Zero) bit to one to enable this feature.
The DS:BOZ bit will be set if Debug Mode is entered due to a trapped 0x0000 instruction. The
debugger must then identify whether this opcode belongs to the original object file or has been
inserted by the debugger as a software breakpoint. If it was part of the object file, the debugger
should use the Instruction Replacement to return to the program, and insert the 0x0000 opcode
in DINST. Executing 0x0000 during Instruction Replacement only performs an ADD R0,R0 oper-
ation without re-entering Debug Mode.
The debugger will typically allow the user to step through the application source or object code,
line by line. This single stepping can be either of step-into or step-over type. Step-into will exe-
cute exactly one instruction and halt the CPU at the start of the next instruction, regardless of
whether this instruction is part of the main program, subroutine, interrupt, or exception. Step-
over will execute the current instruction and any lower-level events generated before the follow-
ing instruction (including subroutines, interrupts, and exceptions).
Step-over in the object code and all single stepping in the source code are implemented by con-
figuring a program breakpoint on the address of the next object code instruction where the
debugger expects to halt.s
Step-into is implemented in OCD hardware and is controlled by the Single Step (SS) bit in the
Development Control register. When Debug Mode is exited by retd, exactly one instruction from
the program memory will be executed before Debug Mode is re-entered. This mechanism works
identically for OCD and Monitor Mode.
If the Event In Control (EIC) bits in DC are written to 0b01, a high-to-low transition on the EVTI
pin will generate a breakpoint. EVTI must stay low for one CPU clock cycle to guarantee that the
breakpoint will trigger. The External Breakpoint (EXB) bit in DS will be set when a breakpoint is
entered due to an event on the EVTI pin.
Some software errors could cause the CPU to get stuck in a state which does not allow Debug
Mode to be entered through the mechanisms described above. An example is if a privileged
mode writes SR:DM to one, without clearing the bit.
To prevent the debugger from hanging indefinitely, the debugger can write the DC:ABORT bit to
one after some timeout period, and force the CPU to enter Debug Mode. The abort command
behaves identical to a debug request, except that the DM bit and any pending exception will be
ignored, regardless of exception priority. The RAR_DBG and RSR_DBG will reflect the last non-
executed instruction, which can aid in locating the error.
If Debug Mode is entered due to an abort command, DS:DBA will be set, as for debug requests.
AVR32
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