AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 96

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.5
9.2.6
32002F–03/2010
Exceptions and Debug Mode
Instruction replacement
Debug Mode has priority over any execution mode, so that breakpoints can be set in exception
and interrupt routines. However, if a breakpoint is set on an instruction which triggers a critical
exception, the breakpoint is flushed. Critical exceptions are exception which are asynchronous
to the CPU (interrupts), exceptions which invalidate the currently fetched instruction (e.g.
instruction address exceptions), and exceptions which indicate that the system has become
unstable and should abort the program flow (e.g. bus error). The complete list of exceptions with
higher priority than Debug Mode are listed in the exception chapter in the AVR32 Architecture
Manual.
If a PC breakpoint, a breakpoint instruction, or a trapped 0x0000 opcode is flushed by an excep-
tion, Debug Mode will not be entered. If another type of breakpoint has triggered, Debug Mode
will be entered on the first instruction in the exception handler.
In the rare cases where the first instruction in a critical exception also triggers a critical exception
(e.g. if EVBA is set incorrectly, triggering an infinite loop of instruction address exceptions), the
debugger must write the DC:ABORT bit to one to halt the CPU and enter Debug Mode to identify
the error.
A convenient way of implementing an unlimited number of instruction breakpoints is letting the
debugger replace an instruction by a breakpoint instruction. This mechanism is only available in
OCD Mode on devices implemented with writeable program memory or writeable instruction
cache. If this instruction executes, Debug Mode will be entered, and the debugger identifies the
breakpointed location. When returning, the breakpoint instruction must be replaced by the origi-
nal instruction. The debugger will write the Instruction Replace (IRP) bit in DC and the
appropriate instruction in the Debug Instruction Register and its corresponding PC value in the
Debug Program Counter (DPC). When retd is executed, PC and SR are restored, but one more
instruction is fetched from the OCD system before returning to fetching from program memory.
Note that instruction replacement operates on word boundaries. The debugger must store the
whole word containing the replaced opcode before inserting the breakpoint instruction. Also note
that DPC should always be written when performing an instruction replacement to ensure the
correct instruction is executed.
The debugger will then perform the following sequence when exiting OCD Mode. Note that
RAR_DBG is accessed through executing CPU instructions through the Debug Instruction regis-
ter (DINST). The same sequence can be used both for compact and extended instructions,
regardless if the extended instruction is unaligned (in which case only the upper halfword of the
instruction is replaced).
1. Write RAR_DBG to the Debug Program Counter.
2. Increment RAR_DBG by 2 or 4, so the register points to the start of the next word in the
3. Write 1 to Instruction Replace (IRP) in DC.
4. Write a retd instruction to DINST. The CPU will exit Debug Mode and stall while waiting
5. Write the stored word to DINST. This instruction is fetched by the CPU, and the CPU
program memory.
for new instructions.
continues normal program execution.
AVR32
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