AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 97

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.6.1
9.2.7
32002F–03/2010
Sleep Mode
Instruction replacement example
Table 9-1 shows an example of a code where the user wants to insert a breakpoint.
Table 9-1.
The tool wants to insert a software breakpoint on the instruction "adc r6,r12,r7" on
PC=0x000016. This is an extended instruction, and only the upper halfword needs to be
replaced by the breakpoint instruction.
If the CPU is in sleep mode, it will not receive clocks nor respond to an OCD request from the
debugger. Thus, if the Debug Request bit in DC is written to one while the CPU is in sleep mode,
the CPU will automatically return to active mode. The instruction following the sleep instruction
will be tagged with an OCD exception, and the CPU will jump directly to Debug Mode. The nor-
mal debug procedure can be followed while executing in Debug Mode. If Debug Mode is entered
from sleep mode, the Stop Status (STP) bit in the Development Status register will be set.
When returning from Debug Mode, the CPU will by default return to the instruction following the
sleep instruction. The debugger can handle this situation in two ways:
Ignore the problem, effectively waking the CPU from sleep mode on a debug request.
PC value
0x000010
0x000012
0x000014
0x000016
0x00001A
1. The upper halfword is contained within the word located at 0x000014, and the debug
2. The debugger writes a breakpoint instruction (opcode 0xD673) to location 0x000016 in
3. When the breakpoint instruction executes, the CPU will enter OCD Mode, and DS:DBS
4. The tool performs a normal sequence of operation in OCD Mode.
5. When the tool is ready to return to normal CPU operation, it reads the RAR_DBG value
6. The tool inserts CPU instructions to DINST to increment RAR_DBG by 2, so it is
7. The tool inserts a "retd" instruction to DINST. The tool will receive a Debug Status mes-
8. The tool writes the return address (0x000016) to the Debug Program Counter (DPC).
9. The tool looks up the stored instruction word (based on the return address) and writes
tool stores this value (0xC0ACF807).
the CPU’s program memory to replace the most significant word of the breakpointed
instruction.
and DS:SWB are set, indicating that OCD Mode is entered due to a software
breakpoint.
to find the return address.
aligned to the next word in the program memory.
sage, which indicates that the CPU has exited OCD Mode, and is now waiting for one
more instruction from the tool.
this value (0xC0ACF807) to the Debug Instruction Register (DINST). The CPU now
resumes normal operation.
Example of a user code section
Opcode
0x0E9C
0x201C
0xC0AC
0xF8070046
0x2027
Instruction
mov r12,r7
sub r12,0x01
rcall label1
adc r6,r12,r7
sub r7,0x02
AVR32
97