AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 89

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.1.2.3
9.1.2.4
9.1.2.5
9.1.2.6
9.1.2.7
32002F–03/2010
Transmit Queue
Flow Control Unit
Breakpoint modules
Program and Data Trace
OS debug support
Trace and watchpoint messages are inserted into the Transmit Queue (TXQ) before being trans-
mitted on the AUX port. This provides some flexibility between the peak rate of trace message
generation and the average rate of message transmission on the AUX port.
The Flow Control Unit (FCU) can bring the CPU into and out of Debug Mode, and control the
CPU operation in Debug Mode. The behavior is controlled by accessing OCD registers.
Debug Mode can be configured as OCD Mode or Monitor Mode. In OCD mode, The CPU
fetches instructions from the Debug Instruction Register. If the register is empty, the CPU is
halted. In Monitor Mode, the CPU fetches debug instructions from a monitor code in the program
memory, and the Debug Instruction Register is not used.
The FCU also handles single stepping by returning the CPU to normal mode, letting the CPU
fetch one instruction from the program memory, and then returning to Debug Mode on the fol-
lowing instruction.
A number of instruction and data breakpoint modules can be configured for run-time monitoring
of the instruction fetches and data accesses by the CPU. The modules can report if the moni-
tored operation matches a predefined address, alternatively, also a data value. The modules
operate on virtual addresses.
A breakpoint will bring the CPU into Debug Mode. Watchpoints are reported to the debugger,
but does not affect CPU operation. A watchpoint can also be configured to start or stop data and
program trace.
The breakpoint modules can be combined to produce a watchpoint or breakpoint. Complex
breakpoint/watchpoint conditions are supported, e.g. trigger when a specific procedure writes a
certain variable with a specific value.
The Program Trace Unit sends Branch Trace Messages to the debugger, which allows the pro-
gram flow to be reconstructed. To keep the amount of debug information low to save bandwidth,
only change of program flow are reported (such as unconditional branches, taken conditional
branches interrupts, exceptions, return operations, and load operations with PC as destination),
hence the term "branch tracing". Messages are typically relative to the previously transmitted
message, to be able to compress information as much as possible. Thus, the trace messages
are sent out in temporal order, and regularly, synchronization messages with uncompressed,
absolute addresses, are transmitted in case synchronization is lost.
The Data Trace Unit similarly traces data accesses, for read or write accesses, or both. Similar
relative address compression and synchronization schemes are used for Data Trace Messages.
Since new trace messages can be generated before the previous ones have been transmitted,
all trace messages are queued before being transmitted by the AUX interface. If the queue over-
flows, the CPU can be halted to avoid losing trace information, or an error message followed by
synchronization trace messages will be transmitted.
Applications developed on an OS platform places special requirements on the OCD controller
and the debug software. For high-level debugging, the user will want to see which process is
AVR32
89