AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 16

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
COMPARE - Cycle Counter Compare Register
BEAR - Bus Error Address Register
MPUARn - MPU Address Register n
MPUPSRn - MPU Privilege Select Register n
MPUCRA / MPUCRB - MPU Cacheable Register A / B
MPUBRA / MPUBRB - MPU Bufferable Register A / B
MPUAPRA / MPUAPRB - MPU Access Permission Register A / B
MPUCR - MPU Control Register
SS_STATUS - Secure State Status Register
SS_ADRF, SS_ADRR, SS_ADR0, SS_ADR1 - Secure State Address Registers
SS_SP_SYS, SS_SP_APP - Secure State SP_SYS and SP_APP Registers
SS_RAR, SS_RSR - Secure State Return Address and Return Status Registers
Used together with COUNT to implement a periodic interrupt for example for an OS timer. The
contents and functionality of this register is described in detail in
COUNT registers” on page
Physical address that caused a Data Bus Error. This register is Read Only. Writes are allowed,
but are ignored.
Registers that define the base address and size of the protection regions. Refer to the AVR32
Architecture Manual for details.
Registers that define which privilege register set to use for the different subregions in each pro-
tection region. Refer to the AVR32 Architecture Manual for details.
Registers that define if the different protection regions are cacheable. Refer to the AVR32 Archi-
tecture Manual for details.
Registers that define if the different protection regions are bufferable. Refer to the AVR32 Archi-
tecture Manual for details.
Registers that define the access permissions for the different protection regions. Refer to the
AVR32 Architecture Manual for details.
Register that control the operation of the MPU. Refer to the AVR32 Architecture Manual for
details.
Register that can be used to pass status or other information from the secure state to the nonse-
cure state. Refer to
Registers used to partition memories into a secure and a nonsecure section. The 10 LSBs must
always be written to zero. Refer to
Read-only registers containing the SP_SYS and SP_APP values. Refer to
State” on page 59
Contains the address and status register of the sscall instruction that called secure state. Also
used when returning to nonsecure state with the retss instruction. Refer to
State” on page 59
for details.
for details.
Section 5. ”Secure State” on page 59
17.
Section 5. ”Secure State” on page 59
for details.
Section 2.6 ”COMPARE and
for details.
Section 5. ”Secure
Section 5. ”Secure
AVR32
16