AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 90

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.1.2.8
9.2
9.2.1
9.2.1.1
32002F–03/2010
CPU Development Support
Debug Mode
Timestamps
Operations in Debug Mode
running at any time, without having to interrupt the CPU or trace the program flow. This is
accomplished through Ownership Trace Messaging, in which the process ID of the running pro-
cess is reported at every process switch. The CPU writes the process ID to an OCD register in
the Ownership Trace Unit, which in turn generates an Ownership Trace Message.
The emulator can tag events with a timestamp when they are extracted from the OCD system
and transmitted to the emulator, to provide timing information for these events when they are
transmitted to the debug host. However, due to the delay of the transmit queue and transmit time
over the AUX port, this timing will have limited accuracy. To compensate for this, the EVTO pin
can be configured to toggle every time a message is inserted into the Transmit Queue, thus indi-
cating very precisely when each event occurs. The emulator would then store a queue of
timestamp tags with each event, and associate each tag with the corresponding message, as
they are extracted on the AUX port.
The OCD system can bring CPU into and out of Debug Mode, and control the CPU operation in
Debug Mode. The behavior is controlled by OCD register configuration, stop commands from
the debugger, or breakpoints. The OCD registers can be accessed by Nexus messages or from
the CPU as memory-mapped registers.
Debug Mode is an execution mode dedicated to application debugging and is not intended for
running application code. Debug Mode can execute a debug code either from an external
debugger through the OCD system (OCD Mode), or from a debug routine in program memory
(Monitor Mode). The debug code will typically read out system registers and information about
the various processes running in the system before restarting.
The Nexus class 2+ compliant OCD system contains breakpoint and trace modules, and other
features for debugging code on the CPU. These features are generally accessible both in OCD
Mode and Monitor Mode. In OCD Mode, the debugger accesses the features through messages
over the AUX debug port, and in Monitor Mode, the CPU accesses the features through mtdr
and mfdr instructions. The OCD system runs at system speed to stay synchronous with the CPU
at all times. If the CPU is in a low-power sleep mode, it is woken up before entering Debug
Mode.
Debug Mode is characterized by the Debug (D) bit in the Status Register (SR) in the CPU.
Debug Mode is a privileged mode, and all legal instructions and memory operations are permit-
ted Illegal opcodes or memory operations which would normally cause an exception will be
ignored in Debug Mode.
The Debug Mode has a dedicated Link and Return Status Register (RAR_DBG and RSR_DBG,
respectively) but no other masked registers. RAR_DBG and RSR_DBG are not observable as
part of the register file, only as system registers. The register file view is mapped according to
the mode bits in the Status Register (M[2:0]). These bits are set to the exception context when
entering Debug Mode, but can be changed freely within Debug Mode by writing to SR. In this
way, different register contexts can be observed and modified, while maintaining the execution
and access privileges of Debug Mode.
AVR32
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