AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 28

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 3-4.
3.9.1
3.9.1.1
32002F–03/2010
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description of events
Handler Address
0x8000_0000
Provided by OCD system
EVBA+0x00
EVBA+0x04
EVBA+0x08
EVBA+0x0C
EVBA+0x10
Autovectored
Autovectored
Autovectored
Autovectored
EVBA+0x14
EVBA+0x50
EVBA+0x18
EVBA+0x1C
EVBA+0x20
EVBA+0x24
EVBA+0x28
EVBA+0x2C
EVBA+0x30
EVBA+0x100
EVBA+0x34
EVBA+0x38
EVBA+0x60
EVBA+0x70
EVBA+0x3C
EVBA+0x40
EVBA+0x44
Reset Exception
Priority and handler addresses for events
The Reset exception is generated when the reset input line to the CPU is asserted. The Reset
exception can not be masked by any bit. The Reset exception resets all synchronous elements
and registers in the CPU pipeline to their default value, and starts execution of instructions at
address 0x8000_0000.
SR = reset_value_of_SREG;
Name
Reset
OCD Stop CPU
Unrecoverable exception
TLB multiple hit
Bus error data fetch
Bus error instruction fetch
NMI
Interrupt 3 request
Interrupt 2 request
Interrupt 1 request
Interrupt 0 request
Instruction Address
ITLB Miss
ITLB Protection
Breakpoint
Illegal Opcode
Unimplemented instruction
Privilege violation
Floating-point
Coprocessor absent
Supervisor call
Data Address (Read)
Data Address (Write)
DTLB Miss (Read)
DTLB Miss (Write)
DTLB Protection (Read)
DTLB Protection (Write)
DTLB Modified
Event source
External input
OCD system
Internal
MPU
Data bus
Data bus
External input
External input
External input
External input
External input
CPU
MPU
MPU
OCD system
Instruction
Instruction
Instruction
UNUSED
Coprocessor
Instruction
CPU
CPU
MPU
MPU
MPU
MPU
UNUSED
Undefined
First non-completed instruction
First non-completed instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC(Supervisor Call) +2
Stored Return Address
First non-completed instruction
PC of offending instruction
PC of offending instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
PC of offending instruction
First non-completed instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
AVR32
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