AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 22

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.5
3.6
3.7
32002F–03/2010
Support for unaligned addresses
Forwarding hardware and hazard detection
Event handling
The read-modify-write instructions memc, mems and memt are performed as a non-interruptable
sequence of read from and write to memory. The load-store section generates the control sig-
nals required to perform this sequence. This sequence takes several clock cycles, so any
following instructions requiring the use of the load-store section must stall until the sequence is
finished. Following instructions that do not use the load-store section will not have to stall even if
the sequence has not finished.
Some memory operations to slow memories, such as memories on the HSB bus, may require
several clock cycles to perform. If required, the CPU pipeline will stall as long as necessary in
order to perform the memory access.
All memory accesses must be performed with the correct alignment according to the data size.
The only exception to this is doubleword accesses, which are performed as two word accesses,
and therefore can be word-aligned. Any other unaligned memory access will cause an Data
Address Exception.
Instruction fetches must be halfword aligned. Any other alignment will cause an Instruction
Address Exception.
Since the register file is read and written in the same pipeline stage, no hazards can occur, and
no forwarding is necessary. The programmer does not need to take any special considerations
regarding data hazards when writing code.
Due to various reasons, the CPU may be required to abort normal program execution in order to
handle special, high-priority events. When handling of these events is complete, normal program
execution can be resumed. Traditionally, events that are generated internally in the CPU are
called exceptions, while events generated by sources external to the CPU are called interrupts.
The possible sources of events are listed in
The AVR32 has a powerful event handling scheme. The different event sources, like Illegal
Opcode and external interrupt requests, have different priority levels, ensuring a well-defined
behaviour when multiple events are received simultaneously. Additionally, pending events of a
higher priority class may preempt handling of ongoing events of a lower priority class.
When an event occurs, the execution of the instruction stream is halted, and execution control is
passed to an event handler at an address specified in
dlers are placed sequentially in the code space starting at the address specified by EVBA, with
four bytes between each handler. This gives ample space for a jump instruction to be placed
there, jumping to the event routine itself. A few critical handlers have larger spacing between
them, allowing the entire event routine to be placed directly at the address specified by the
EVBA-relative offset generated by hardware. All external interrupt sources have autovectored
interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify
the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giv-
ing an offset of maximum 16384 bytes. The target address of the event handler is calculated as
(EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception
code segments must be set up appropriately.
Table 3-4 on page
Table 3-4 on page
28.
28. Most of the han-
AVR32
22