AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 94

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.4.1
9.2.4.2
9.2.4.3
9.2.4.4
32002F–03/2010
Debug request
Program counter breakpoint
Data address or value breakpoint
breakpoint instruction
The debugger may want to stop CPU operation, unrelated to current instruction execution, e.g. if
the user presses a "STOP" button in the debug tool GUI. The debugger will then write the Debug
Request (DBR) bit in the Development Control Register (DC). This causes the CPU to enter
Debug Mode on the next instruction to be executed, before execution.
The Program Counter breakpoints can be configured to halt the CPU when executing code at a
specific address, or address range. This will cause the CPU to be halted before the break-
pointed instruction is executed.
The Ignore First Match (IFM) bit in the Development Control (DC) register should be written to
one before exiting Debug Mode, to avoid re-triggering the program breakpoint. This bit only pre-
vents program breakpoints from re-triggering. If the instruction causes a breakpoint for another
reason (e.g. a breakpoint instruction or a data breakpoint), Debug Mode will be re-entered.
CPU memory accesses can be monitored by data breakpoint comparators in the OCD system. If
the access matches a set of predefined conditions (e.g. address, value, or access type), Debug
Mode is entered after the memory operation completes, but before the next instruction is
executed.
Data breakpoints are precise, halting on the instruction immediately after the memory operation
which caused the breakpoint. The CPU will return to the first non-executed instruction when a
retd is executed.
The breakpoint instruction is programmed along with the object code into the program memory
or instruction cache, and is decoded by the CPU. When this instruction is scheduled for execu-
tion and Debug Mode is enabled, the CPU will enter Debug Mode. If Debug Mode is disabled
(e.g. masked by the DM bit in the Status Register, or DBE in DC is zero), the breakpoint instruc-
tion will execute as a nop (no operation).
For devices based on volatile program memory, the breakpoint instruction can be dynamically
inserted into the code by the debug tool, enabling an unlimited number of program breakpoints
in the code. This involves replacing an existing opcode with a breakpoint instruction. The
replaced opcode has to be re-inserted before exiting Debug Mode. Note that this is only possible
in OCD Mode.
For devices based on non-volatile program memory, the breakpoint instruction can be statically
compiled or linked into the code before downloading, marking all points the program can be
halted. Debug Mode will be entered for all breakpoints (if Debug Mode is enabled), and the
debugger would return immediately if it does not want to halt at a particular breakpoint location in
the code.
The breakpoint will be taken before the breakpoint instruction is actually executed. This has the
effect that the CPU will return from Debug Mode to the same breakpoint instruction, re-entering
Debug Mode immediately, unless the OCD system is configured to modify the return address or
replace the breakpoint instruction from the instruction flow. The IFM bit does not have an effect
when Debug Mode returns to a breakpoint instruction.
AVR32
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