AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 114

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.3.3.3
9.3.3.4
9.3.3.5
32002F–03/2010
Message rules
Clock and frame rate
Example
MDO is valid whenever MSEO does not indicate "idle".
Fixed length packets are implicitly recognized from the message format, and are not required to
end on a port boundary. Thus, packets may also start within a port boundary if following a fixed
length packet. The end of variable length packets is identified through the MSEO pins, and to
identify the end of the packet uniquely, these packets must end on a port boundary. If neces-
sary, the packet must be stuffed with zeroes to align the end to a port boundary. Variable length
packets may be truncated by omitting leading zeroes so that the packet ends on the first possi-
ble port boundary.
In single datarate mode (default), MDO and MSEO should be sampled by an external tool on the
rising edge of MCKO. In double datarate mode, the MCKO clock runs at half frequency, so MDO
and MSEO should be sampled on both edges of MCKO. This is configured by the Double Dat-
arate bit in the AUX Port Control Register.
It is also possible to reduce the frequency of the AUX port compared to the CPU clock by writing
the AXC:LS and AXC:DIV bits. If LS=1, the DIV value selects the frame rate of the AUX port:
f
If LS=1 and DIV=0, f
This can be combined with the single or dual datarate mode, as described above. In either case,
the sampling edge will be as close to the middle of the MDO data frame as possible. The duty
cycle of the MCKO clock will stay within the 40-60 duty cycle requirement of the Nexus standard
for all settings apart from DIV=2.
Figure 9-5 shows an example of transmission of a Program Trace Indirect Branch message. The
TCODE is fixed at 6 bits (=4 for PTIB), followed by a fixed-length packet (EVT-ID = 2), and a
variable-length packet (I-CNT = 63). I-CNT is stuffed with zeroes to fit the port boundary. Finally,
the variable packet U-ADDR (=5) is transmitted. Since this leading zeroes of this packet can be
truncated, it fits within a single frame.
AUX
• The MSEO pins behave the following way ("x" means "don’t care"):
• 0b11 followed by 0b00 indicates SOM
• 0b0x followed by 0b11 indicates EOM
• 0b00 followed by 0b01 indicates EVLP
• MSEO is 0b00 at all other clocks during transmission of a message
• MSEO is 0b11 at all clocks when idle.
= f
CPU
/(DIV+1)
AUX
= f
CPU
/2.
AVR32
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