AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 92

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.2.1
9.2.3
32002F–03/2010
OCD Mode
Debugging a monitor code
areas. All other exceptions and interrupts are masked by default when entering Monitor Mode,
but the monitor code can explicitly unmask interrupts to allow critical interrupts to be serviced
while the system is being debugged.
The monitor code will typically communicate with an external debug tool, or (in cases of
advanced systems like PDA’s) a debug tool running within the application (self-hosted debug-
ger). Communication with the external tool may take place over any communication link present
in that device (e.g. USB, RS232), if such a communication line can be reserved for debug
purposes.
Alternatively, the Debug Communication Mechanism in the OCD system can be used to commu-
nicate between the CPU and emulator over the JTAG port. This is a set of OCD registers which
can be written by the CPU or emulator, allowing a communication protocol to be developed in
software. This mechanism can be used in any privileged CPU mode, including OCD Mode.
Monitor Mode is exited with the retd instruction.
Each execution mode has a mask bit in SR, which indicates if a request to enter that mode will
be taken or masked. The default priority of modes are reflected in these bits: When entering an
execution mode, modes of the same or lower priority are masked. Privileged modes can over-
ride the mask, to dynamically change priorities (e.g. to allow critical interrupts to be serviced).
By default, Debug Mode has priority above all other execution modes. This implies that any
supervisor or user code can be interrupted by Debug Mode. Other modes can be explicitly
unmasked by a monitor code to allow critical interrupts to be serviced. By default, Debug Mode
is masked by the Debug Mask (DM) bit in SR when executing in Monitor Mode. The Monitor
Mode can stack away the RAR_DBG and RSR_DBG and then explicitly clear the DM bit to
enable Debug Mode to be re-entered. If a debug exception occurs in Monitor Mode, the OCD
system will bring the CPU into OCD Mode, even if the MM bit is set. This allows Monitor Mode
programs to be debugged.
If the Monitor Mode (MM) bit in the Development Control register (DC) is cleared, the CPU will
enter Debug Mode in OCD Mode. When the CPU is in OCD Mode, the Debug Status (DBS) bit
in the Development Status (DS) register is set, in addition to the D bit in SR in the CPU. OCD
Mode is similar to Monitor Mode, except that instructions are fetched from the OCD system.
OCD instructions are loaded by the debug tool by writing the opcode to the Debug Instruction
register (DINST). Once an instruction is written to DINST, the CPU will fetch it, and the Instruc-
tion Complete bit in DS (DS:INC) will be cleared until the CPU has completed the operation. The
CPU is then halted until DINST is written again.
The first instruction entered must be aligned to the MSB of DINST. A sequence of instructions
can be entered to DINST one word at a time, in the same sequence they would appear in pro-
gram memory, i.e. they do not need to be word aligned. If the upper halfword of an extended
instruction is written to the lower halfword of DINST, the lower halfword of the instruction is writ-
ten as the upper halfword of DINST in the next access. If the last instruction in a sequence is
written to the upper halfword of DINST, the lower halfword should be written with a nop opcode.
See Figure 9-3 for an illustration of a sequence of operations used to execute instructions in
OCD Mode.
AVR32
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