AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 23

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.7.1
32002F–03/2010
Exceptions and interrupt requests
The same mechanisms are used to service all different types of events, including external inter-
rupt requests, yielding a uniform event handling scheme.
Each pipeline stage has a pipeline register that holds the exception requests associated with the
instruction in that pipeline stage. This allows the exception request to follow the contaminated
instruction through the pipeline. Exceptions are detected in two different pipeline stages. The EX
stage detects all data-address related exceptions (DTLB Protection and Data Address). All other
exceptions, including interrupts, are detected in the ID stage. When an exception is detected in
EX, the EX stage and all upstream stages are flushed.
Generally, all exceptions, including breakpoint, have the failing instruction as restart address.
This allows a fixup exception routine to correct the error and restart the instruction. Interrupts
(INT0-3, NMI) have the address of the first non-completed instruction as restart address.
When an event other than scall or debug request is received by the core, the following actions
are performed atomically:
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2 or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.
Note that event priorities are only used to determine which event handler to call first when multi-
ple events are received simultaneously. Once control is passed on to the event handler,
handling of pending and lower priority events may be initiated if not masked.
For instance, it is possible to make a supervisor call (SCALL) from an interrupt level 0 handler,
even though the priority of a supervisor call event is lower than the active interrupt level 0 event.
1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM and
2. When a request is accepted, the Status Register and Program Counter of the current
3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis-
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit and Bus
Error) can not be masked. When an event is accepted, hardware automatically sets the
mask bits corresponding to all sources with equal or lower priority. This inhibits accep-
tance of other events of the same or lower priority, except for the critical events listed
above. Software may choose to clear some or all of these bits after saving the neces-
sary state if other priority schemes are desired. It is the event source’s responsibility to
ensure that their events are left pending until accepted by the CPU.
context is stored to the system stack. If the event is an INT0, INT1, INT2 or INT3, regis-
ters R8-R12 and LR are also automatically stored to stack. Storing the Status Register
ensures that the core is returned to the previous execution mode when the current
event handling is completed. When exceptions occur, both the EM and GM bits are set,
and the application may manually enable nested exceptions if desired by clearing the
appropriate bit. Each exception handler has a dedicated handler address, and this
address uniquely identifies the exception source.
ter file bank is selected. The address of the event handler, as shown in Table 3-4, is
loaded into the Program Counter.
AVR32
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