PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 121

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

14.2
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN bit (T1CON Register). The oscillator is a
low power oscillator rated up to 200 kHz. Refer to
Section 12.0, Timer1 Module for Timer1 oscillator
details.
14.3
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The TMR3
Interrupt, if enabled, is generated on overflow, which is
latched in interrupt flag bit TMR3IF (PIR registers). This
interrupt can be enabled/disabled by setting/clearing
TMR3 interrupt enable bit TMR3IE (PIE registers).
TABLE 14-1:
 2002 Microchip Technology Inc.
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Name
Timer1 Oscillator
Timer3 Interrupt
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
GIE/ GIEH PEIE/GIEL
RD16
RD16
Bit 7
—
—
—
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3ECCP1 T3CKPS1 T3CKPS0
CMIF
CMIE
CMIP
Bit 6
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR0IE
Bit 5
—
—
—
INT0IE
EEIE
EEIP
Bit 4
EEIF
Preliminary
T3CCP1
BCLIF
BCLIE
BCLIP
RBIE
Bit 3
14.4
If the CCP module is configured in Compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature. If
Timer3 is running in Asynchronous Counter mode, this
RESET operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation,
becomes the period register for Timer3. Refer to
Section 15.0, “Capture/Compare/PWM (CCP) Modules
for CCP details.
Note:
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
TMR0IF
LVDIF
LVDIE
LVDIP
Bit 2
Resetting Timer3 Using a CCP
Trigger Output
The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR registers).
TMR3IF ECCP1IF -0-0 0000 -0-0 0000
TMR3IE ECCP1IE -0-0 0000 -0-0 0000
TMR3IP ECCP1IP -0-0 0000 -0-0 0000
the
INT0IF
Bit 1
CCPR1H:CCPR1L
Bit 0
RBIF
PIC18FXX8
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
POR,
BOR
DS41159B-page 119
registers
Value on
RESETS
all other
pair