PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 81

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

8.1
The INTCON Registers are readable and writable reg-
isters, which contain various enable, priority, and flag
bits. Because of the number of interrupts to be con-
trolled, PIC18FXX8 devices have three INTCON regis-
ters. They are detailed in Register 8-1 through
Register 8-3.
REGISTER 8-1:
 2002 Microchip Technology Inc
INTCON Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON REGISTER
Legend:
R = Readable bit
- n = Value at POR
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN (RCON<7>) = 1:
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN (RCON<7>) = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software by reading PORTB)
0 = The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
1 = Enables all high priority interrupts
0 = Disables all priority interrupts
GIE/GIEH PEIE/GIEL
R/W-0
R/W-0
TMR0IE
R/W-0
Preliminary
W = Writable bit
’1’ = Bit is set
INT0IE
R/W-0
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
RBIE
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows software polling.
TMR0IF
R/W-0
PIC18FXX8
x = Bit is unknown
INT0IF
R/W-0
DS41159B-page 79
R/W-x
RBIF
bit 0