PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 84

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX8
8.2
The Peripheral Interrupt Request (PIR) registers con-
tain the individual flag bits for the peripheral interrupts
(Register 8-4 through Register 8-6). Due to the number
of peripheral interrupt sources, there are three Periph-
eral Interrupt Request (Flag) registers (PIR1, PIR2,
PIR3).
REGISTER 8-4:
DS41159B-page 82
PIR Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (PIR1)
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 =The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0 =The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
Legend:
R = Readable bit
- n = Value at POR
PSPIF
R/W-0
(1)
is unimplemented and reads as ’0’.
R/W-0
ADIF
RCIF
Preliminary
R-0
W = Writable bit
’1’ = Bit is set
TXIF
R-0
Note 1: Interrupt flag bits are set when an interrupt
2: User software should ensure the appropri-
SSPIF
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON register).
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
(1)
CCP1IF
R/W-0
 2002 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
TMR1IF
R/W-0
bit 0