PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 155

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 17-5:
 2002 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPCON2: MSSP CONTROL REGISTER 2 (I
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note:
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
0 = Acknowledge sequence IDLE
RCEN: Receive Enable bit (Master Mode only)
1 = Enables Receive mode for I
0 = Receive IDLE
PEN: STOP Condition Enable bit (Master mode only)
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition IDLE
RSEN: Repeated START Condition Enabled bit (Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins.
0 = Repeated START condition IDLE
SEN: START Condition Enabled/Stretch Enabled bit
In Master mode:
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition IDLE
In Slave mode:
1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)
0 = Clock stretching is enabled for Slave Transmit only (Legacy mode)
Legend:
R = Readable bit
- n = Value at POR reset
Note:
R/W-0
GCEN
Automatically cleared by hardware.
Automatically cleared by hardware.
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
ACKSTAT
R/W-0
ACKDT
R/W-0
Preliminary
W = Writable bit
’1’ = Bit is set
2
C
ACKEN
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
2
R/W-0
RCEN
C MODE)
R/W-0
2
PEN
C module is not in the IDLE
PIC18FXX8
x = Bit is unknown
R/W-0
RSEN
DS41159B-page 153
R/W-0
SEN
bit 0