PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 128

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX8
15.4
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.3.
FIGURE 15-3:
A PWM output (Figure 15-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-4:
DS41159B-page 126
Note:
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock,
CCPR1L (Master)
CCPR1H (Slave)
Comparator
Duty Cycle Registers
TMR2 = PR2
PR2
TMR2
PWM Mode
Comparator
or 2 bits of the prescaler, to create 10-bit time-base.
Duty Cycle
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Period
(Note 1)
TMR2 = Duty Cycle
Clear Timer,
Set CCP1 pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
TMR2 = PR2
CCP1CON<5:4>
R
S
Q
TRISC<2>
RC2/CCP1
Preliminary
15.4.1
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the
following formula.
EQUATION 15-1:
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPR1L into
15.4.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time.
EQUATION 15-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
cycle = 0%, the CCP1 pin will not be set)
CCPR1H
Note:
PWM duty cycle =(CCPR1L:CCP1CON<5:4>) •
PWM period = [(PR2) + 1] • 4 • T
The Timer2 postscaler (see Section 13.0)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a servo update rate at a
different frequency than the PWM output.
PWM PERIOD
PWM DUTY CYCLE
T
(TMR2 prescale value)
OSC
 2002 Microchip Technology Inc.
• (TMR2 prescale value)
OSC
•