PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 379

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

2002 Microchip Technology Inc.
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a STOP
Bus Collision During a STOP
Bus Collision During START
Bus Collision During START
Bus Collision for Transmit and
Capture/Compare/PWM
CLKO and I/O .......................................................... 338
Clock Synchronization ............................................. 161
External Clock .......................................................... 337
First START bit Timing ............................................. 169
I
I
I
I
I
I
I
I
I
I
Low Voltage Detect .................................................. 258
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F248
Parallel Slave Port Read Waveforms ....................... 106
Parallel Slave Port Write Waveforms ....................... 105
Repeat START Condition ........................................ 170
RESET, Watchdog Timer (WDT), Oscillator
Slave Mode General Call Address Sequence
Slave Synchronization ............................................. 147
Slow Rise Time (MCLR Tied to V
SPI Master Mode (CKE = 0) .................................... 343
SPI Master Mode (CKE = 1) .................................... 344
SPI Mode (Master Mode) ......................................... 146
SPI Mode (Slave Mode with CKE = 0) ..................... 148
SPI Mode (Slave Mode with CKE = 1) ..................... 148
SPI Slave Mode (CKE = 0) ...................................... 345
SPI Slave Mode (CKE = 1) ...................................... 346
STOP Condition Receive or Transmit Mode ............ 175
Time-out Sequence on POR w/ PLL Enabled
Time-out Sequence on Power-up
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 347
C Bus START/STOP bits ...................................... 347
C Master Mode (Reception, 7-bit Address) ........... 173
C Master Mode (Transmission, 7 or
C Slave Mode (Transmission,
C Slave Mode (Transmission,
C Slave Mode SEN = 1 (Reception,
C Slave Mode with SEN = 0 (Reception,
C Slave Mode with SEN = 0 (Reception,
C Slave Mode with SEN = 1 (Reception,
START Condition (Case 1) .............................. 179
START Condition (Case2) ............................... 179
Condition (Case 1) ........................................... 180
Condition (Case 2) ........................................... 180
Condition (SCL = 0) ......................................... 178
Condition (SDA Only) ....................................... 177
Acknowledge .................................................... 176
(CCP1 and ECCP1) ......................................... 341
10-bit Address) ................................................. 172
10-bit Address) ................................................. 159
7-bit Address) ................................................... 157
10-bit Address) ................................................. 163
10-bit Address) ................................................. 158
7-bit Address) ................................................... 156
7-bit Address) ................................................... 162
and PIC18F458) ............................................... 342
Start-up Timer (OST), Power-up Timer
(PWRT) ............................................................ 339
(7 or 10-bit Address Mode) .............................. 164
Via RC Network) ................................................ 29
(MCLR Tied to V
(MCLR Not Tied to V
2
2
C Bus Data ........................................ 349
C Bus START/STOP bits .................. 349
DD
Via RC Network) ................ 29
DD
): Case 1 ....................... 28
DD
Preliminary
Timing Diagrams and Specifications ............................... 337
TSTFSZ ........................................................................... 317
TXSTA Register
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 340
Transition Between Timer1 and OSC1
Transition Between Timer1 and OSC1
Transition Between Timer1 and OSC1
Transition from OSC1 to Timer1 Oscillator ................ 21
USART Asynchronous Reception ............................ 190
USART Asynchronous Transmission ...................... 188
USART Asynchronous Transmission
USART Synchronous Receive (Master/Slave) ........ 351
USART Synchronous Reception
USART Synchronous Transmission ........................ 192
USART Synchronous Transmission
USART Synchronous Transmission
Wake-up from SLEEP via Interrupt .......................... 271
A/D Conversion Requirements ................................ 353
Capture/Compare/PWM Requirements
CLKO and I/O Timing Requirements ....................... 338
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements (CKE = 1) 346
External Clock Timing Requirements ...................... 337
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 338
RESET, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External
USART Synchronous Transmission
BRGH bit ................................................................. 183
2
2
C Bus Data Requirements (Slave Mode) .............. 348
C Bus START/STOP bits Requirements
(MCLR Not Tied to V
(MCLR Tied to V
(HS with PLL) .................................................... 22
(HS, XT, LP) ...................................................... 21
(RC, EC) ............................................................ 22
(Back to Back) ................................................. 188
(Master Mode, SREN) ..................................... 193
(Master/Slave) ................................................. 351
(Through TXEN) .............................................. 192
(CCP1 and ECCP1) ......................................... 341
(Master Mode, CKE = 0) .................................. 343
(Master Mode, CKE = 1) .................................. 344
(Slave Mode, CKE = 0) .................................... 345
(Slave Mode) ................................................... 347
Requirements .................................................. 349
(PIC18F248 and PIC18F458) .......................... 342
Timer, Power-up Timer, Brown-out Reset
and Low Voltage Detect Requirements ........... 339
Clock Requirements ........................................ 340
Requirements .................................................. 351
2
2
C Bus Data Requirements ................ 350
C Bus START/STOP bits
DD
PIC18FXX8
Via RC Network) ................ 28
DD
): Case 2 ...................... 28
DS41159B-page 377