PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 177

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 17-24:
17.4.14
While in SLEEP mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
17.4.15
A RESET disables the MSSP module and terminates
the current transfer.
17.4.16
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I
bus may be taken when the P bit (SSPSTAT<4>) is set,
or the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is the
expected output level. This check is performed in
hardware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
 2002 Microchip Technology Inc.
SLEEP OPERATION
EFFECT OF A RESET
MULTI-MASTER MODE
Note: T
SCL
SDA
Falling edge of
9th clock
Write to SSPCON2
BRG
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
= one baud rate generator period.
Set PEN
2
C module can receive
T
T
BRG
BRG
SDA asserted low before rising edge of clock
to setup STOP condition.
T
SCL brought high after T
BRG
Preliminary
2
C
P
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
T
BRG
17.4.17
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA, by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag BCLIF and reset the I
port to its IDLE state (Figure 17-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I
asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I
by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is IDLE and the S and P bits are
cleared.
2
C bus is free, the user can resume communication by
PEN bit (SSPCON2<2>) is cleared by
2
hardware and the SSPIF bit is set
BRG
BRG
C bus is free, the user can resume communication
, followed by SDA = 1 for T
MULTI -MASTER
COMMUNICATION, BUS COLLISION
AND BUS ARBITRATION
PIC18FXX8
BRG
DS41159B-page 175
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2
C
C