PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 275

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

24.4.1
The user memory may be read to or written from any
location using the Table Read and Table Write instruc-
tions. The device ID may be read with Table Reads.
The configuration registers may be read and written
with the Table Read and Table Write instructions.
In User mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from Table Writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
Table Reads. For a block of user memory with the
EBTRn bit set to ‘0’, a Table Read instruction that
executes from within that block is allowed to read. A
Table Read instruction that executes from a location
outside of that block is not allowed to read, and will
result in reading ‘0’s. Figures 24-4 through 24-6
illustrate Table Write and Table Read protection.
FIGURE 24-4:
2002 Microchip Technology Inc.
TBLPTR = 000FFF
Results: All Table Writes disabled to Blockn whenever WRTn = ‘0’
Register Values
PC = 001FFE
PC = 004FFE
PROGRAM MEMORY
CODE PROTECTION
TABLE WRITE (WRTn) DISALLOWED
Program Memory
Preliminary
TBLWT *
TBLWT *
Note:
000000h
0001FFh
005FFFh
006000h
007FFFh
000200h
001FFFh
002000h
003FFFh
004000h
.
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRTB,EBTRB = 11
WRT0,EBTR0 = 01
WRT1,EBTR1 = 11
WRT2,EBTR2 = 11
WRT3,EBTR3 = 11
PIC18FXX8
DS41159B-page 273