PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 154

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX8
REGISTER 17-4:
DS41159B-page 152
bit 7
bit 6
bit 5
bit 4
bit 3-0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note:
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I
1110 = I
1011 = I
1000 = I
0111 = I
0110 = I
Note:
Legend:
R = Readable bit
- n = Value at POR
SSPCON1: MSSP CONTROL REGISTER1 (I
WCOL
R/W-0
a transmission to be started (must be cleared in software)
cleared in software)
be cleared in software)
2
2
2
2
2
2
C Slave mode, 10-bit address with START and STOP bit interrupts enabled
C Slave mode, 7-bit address with START and STOP bit interrupts enabled
C Firmware Controlled Master mode (Slave IDLE)
C Master mode, clock = F
C Slave mode, 10-bit address
C Slave mode, 7-bit address
When enabled, the SDA and SCL pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved, or implemented in
SPI mode only.
SSPOV
R/W-0
W = Writable bit
’1’ = Bit is set
SSPEN
R/W-0
Preliminary
OSC
R/W-0
CKP
/ (4 * (SSPADD+1))
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
SSPM3
R/W-0
2
C MODE)
2
SSPM2
C conditions were not valid for
R/W-0
 2002 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
SSPM0
R/W-0
bit 0