PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 97

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

9.2
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= ‘1’) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= ‘0’)
will make the corresponding PORTB pin an output ( i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATB register,
read and write the latched output value for PORTB.
EXAMPLE 9-2:
FIGURE 9-4:
 2002 Microchip Technology Inc.
CLRF
CLRF
MOVLW
MOVWF
Note 1: I/O pins have diode protection to V
RBPU
Data Bus
WR LATB
or
WR PORTB
WR TRISB
RD TRISB
RD LATB
RBx/INTx
RD PORTB
Set RBIF
From other
RB7:RB4 pins
2: To enable weak pull-ups, set the appropriate TRIS
(2)
PORTB, TRISB and LATB Registers
bit(s) and clear the RBPU bit (INTCON2 register).
PORTB
LATB
0CFh
TRISB
Data Latch
TRIS Latch
D
D
CK
CK
INITIALIZING PORTB
RB7:RB4 PINS BLOCK
DIAGRAM
Q
Q
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB3:RB0 as inputs
; RB5:RB4 as outputs
; RB7:RB6 as inputs
Q
Q
Latch
EN
EN
D
D
TTL
Input
Buffer
DD
and V
V
P
DD
Weak
Pull-up
I/O pin
SS
Buffer
.
Q1
Q3
ST
(1)
Preliminary
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2 register). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON register).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 9-5:
Note 1: I/O pins have diode protection to V
RBPU
Data Bus
WR TRIS
RD TRIS
RD Port
RBx/INTx
WR Port
Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
Clear flag bit RBIF.
2: To enable weak pull-ups, set the appropriate TRIS
(2)
bit(s) and clear the RBPU bit (INTCON2 register).
TRIS Latch
Data Latch
D
D
CK
CK
RB1:RB0 PINS BLOCK
DIAGRAM
Q
Q
PIC18FXX8
Q
Schmitt Trigger
Buffer
EN
DS41159B-page 95
D
DD
TTL
Input
Buffer
and V
V
P
DD
SS
Weak
Pull-up
I/O pin
.
(1)