PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 72

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX8
6.4
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
bulk erased. Word erase in the FLASH array is not
supported.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the FLASH pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal
FLASH. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
EXAMPLE 6-2:
DS41159B-page 70
Required
Sequence
ERASE_ROW
Erasing FLASH Program memory
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
ERASING A FLASH PROGRAM MEMORY ROW
upper (CODE_ADDR)
TBLPTRU
high (CODE_ADDR)
TBLPTRH
low (CODE_ADDR)
TBLPTRL
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
EECON1,FREE
INTCON,GIE
55h
EECON2
0AAh
EECON2
EECON1,WR
INTCON,GIE
Preliminary
; load TBLPTR with the base
; address of the memory block
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
; write 55H
; write 0AAH
; start erase (CPU stall)
; NOP needed for proper code execution
; re-enable interrupts
6.4.1
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Note:
Load table pointer with address of row being
erased.
Set the EECON1 register for the erase operation:
• set the EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set the WREN bit to enable writes;
• set the FREE bit to enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase
(about 2 ms using internal timer).
Execute a NOP.
Re-enable interrupts.
A NOP is needed after the WR command to
ensure proper code execution.
FLASH PROGRAM MEMORY
ERASE SEQUENCE
 2002 Microchip Technology Inc.