PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 22

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX8
2.6
The PIC18FXX8 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For the PIC18FXX8 devices, this alternate clock source
is the Timer1 oscillator. If a low frequency crystal
(32 kHz, for example) has been attached to the Timer1
oscillator pins and the Timer1 oscillator has been
enabled, the device can switch to a Low Power Execu-
tion mode. Figure 2-6 shows a block diagram of the sys-
tem clock sources. The clock switching feature is
enabled by programming the Oscillator Switching
Enable (OSCSEN) bit in Configuration register,
CONFIG1H, to a ’0’. Clock switching is disabled in an
erased device. See Section 12.2 for further details of
the Timer1 oscillator, and Section 24.1 for Configuration
Register details.
FIGURE 2-6:
REGISTER 2-1:
DS41159B-page 20
Oscillator Switching Feature
bit 7-1
bit 0
OSC2
OSC1
T1OSO
T1OSI
Note:
DEVICE CLOCK SOURCES
bit 7
Unimplemented: Read as '0'
SCS: System Clock Switch bit
When OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When OSCSEN is clear or T1OSCEN is clear:
Bit is forced clear
Legend:
R = Readable bit
- n = Value at POR
OSCCON REGISTER
U-0
—
I/O pins have diode protection to V
Timer 1 Oscillator
Main Oscillator
PIC18FXX8
U-0
—
SLEEP
T1OSCEN
Enable
Oscillator
U-0
Preliminary
—
W = Writable bit
’1’ = Bit is set
DD
U-0
Clock Source Option
for Other Modules
4 x PLL
—
2.6.1
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON register), controls the clock switching. When
the SCS bit is ’0’, the system clock source comes from
the main oscillator selected by the FOSC2:FOSC0 con-
figuration bits. When the SCS bit is set, the system clock
source comes from the Timer1 oscillator. The SCS bit is
cleared on all forms of RESET.
T
and V
T
Note:
T
OSC
1
P
SS
.
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
T
U-0
The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 control register
(T1CON). If the Timer1 oscillator is not
enabled, any write to the SCS bit will be
ignored (SCS bit forced cleared) and the
main oscillator continues to be the system
clock source.
OSC
—
SYSTEM CLOCK SWITCH BIT
/4
Source
Clock
U-0
—
 2002 Microchip Technology Inc.
x = Bit is unknown
T
U-0
SCLK
—
R/W-0
SCS
bit 0