PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 151

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

17.3.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal
transmit/receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from SLEEP.
17.3.9
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 17-2:
 2002 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
TRISF
SSPBUF
SSPCON
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by the MSSP in SPI mode.
Name
mode,
SLEEP OPERATION
EFFECTS OF A RESET
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
TRISF7
WCOL
PSPIF
PSPIE
PSPIP
Bit 7
SMP
REGISTERS ASSOCIATED WITH SPI OPERATION
the
module
TRISF6
SSPOV
ADIF
ADIE
ADIP
Bit 6
CKE
will
TRISF5
SSPEN
RCIF
RCIE
RCIP
Bit 5
D/A
continue
TRISF4
INT0IE
TXIE
TXIP
Bit 4
TXIF
CKP
P
Preliminary
to
TRISF3
SSPM3
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
S
17.3.10
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
There is also a SMP bit, which controls when the data
is sampled.
Standard SPI Mode
TMR0IF
CCP1IE
CCP1IP
CCP1IF
TRISF2
SSPM2
Bit 2
R/W
Terminology
0, 0
0, 1
1, 0
1, 1
BUS MODE COMPATIBILITY
TMR2IE
TMR2IP
TMR2IF
TRISF1
SSPM1
INT0IF
Bit 1
UA
SPI BUS MODES
TMR1IE 0000 0000 0000 0000
TMR1IP 0111 1111 0111 1111
TMR1IF
TRISF0
SSPM0
RBIF
Bit 0
BF
PIC18FXX8
CKP
Control Bits State
0
0
1
1
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
POR, BOR
Value on
DS41159B-page 149
CKE
Value on
all other
RESETS
1
0
1
0