PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 232

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX8
19.7.1
As already mentioned, the Time Quanta is a fixed unit
derived from the oscillator period and baud rate pres-
caler. Its relationship to T
is shown in Example 19-2.
EXAMPLE 19-2:
The frequencies of the oscillators in the different nodes
must be coordinated in order to provide a system wide
specified nominal bit time. This means that all oscilla-
tors must have a T
It should also be noted that although the number of T
is programmable from 4 to 25, the usable minimum is
8 T
guaranteed to operate correctly.
19.7.2
This part of the bit time is used to synchronize the var-
ious CAN nodes on the bus. The edge of the input sig-
nal is expected to occur during the sync segment. The
duration is 1 T
DS41159B-page 230
T
T
Nominal Bit Rate (bits/s) = 1 / T
CASE 1:
For F
Nominal Bit Time = 8 T
T
T
Nominal Bit Rate = 1 / 10
CASE 2:
For F
Nominal Bit Time = 8 T
T
T
Nominal Bit Rate = 1 / 1.6 * 10
CASE 3:
For F
Nominal Bit Time = 25 T
T
T
Nominal Bit Rate = 1 / 1.28 * 10
Q
BIT
Q
BIT
Q
BIT
Q
BIT
Q
= (2*1) / 16 = 0.125 µs (125 ns)
= (2*2) / 20 = 0.2 µs (200 ns)
= (2*64) / 25 = 5.12 µs
(µs) = (2 * (BRP+1)) / F
. A bit time of less than 8 T
(µs) = T
= 8 * 0.125 = 1 µs (10
= 8 * 0.2 = 1.6 µs (1.6 * 10
= 25 * 5.12 = 128 µs (1.28 * 10
OSC
OSC
OSC
= 16 MHz, BRP<5:0> = 00h, and
= 20 MHz, BRP<5:0> = 01h, and
= 25 MHz, BRP<5:0> = 3Fh, and
TIME QUANTA
SYNCHRONIZATION SEGMENT
Q
Q
.
(µs) * number of T
OSC
CALCULATING T
NOMINAL BIT RATE AND
NOMINAL BIT TIME
that is an integral divisor of T
Q
Q
BIT
Q
:
:
-6
:
-6
OSC
= 10
and the Nominal Bit Rate
s)
-6
(MHz)
-6
BIT
6
-4
s = 625,000 bits/s
Q
bits/s (1 Mb/s)
S
= 7813 bits/s
Q
)
per bit interval
-4
(7.8 Kb/s)
(625 Kb/s)
in length is not
s)
Q
,
Preliminary
Q
Q
.
19.7.3
This part of the bit time is used to compensate for phys-
ical delay times within the network. These delay times
consist of the signal propagation time on the bus line
and the internal delay time of the nodes. The length of
the Propagation Segment can be programmed from
1 T
19.7.4
The Phase Buffer Segments are used to optimally
locate the sampling point of the received bit, within the
nominal bit time. The sampling point occurs between
phase segment 1 and phase segment 2. These seg-
ments can be lengthened or shortened by the resyn-
chronization process. The end of phase segment 1
determines the sampling point within a bit time. Phase
segment 1 is programmable from 1 T
tion. Phase segment 2 provides delay before the next
transmitted data transition and is also programmable
from 1 T
requirements, the actual minimum length of phase seg-
ment 2 is 2 T
greater of phase segment 1 or the Information
Processing Time (IPT).
19.7.5
The Sample Point is the point of time at which the bus
level is read and the value of the received bit is deter-
mined. The sampling point occurs at the end of phase
segment 1. If the bit timing is slow and contains many
T
line at the sample point. The value of the received bit is
determined to be the value of the majority decision of
three values. The three samples are taken at the sam-
ple point, and twice before, with a time of T
each sample.
19.7.6
The Information Processing Time (IPT) is the time seg-
ment, starting at the sample point that is reserved for
calculation of the subsequent bit level. The CAN spec-
ification defines this time to be less than or equal to
2 T
Thus, phase segment 2 must be at least 2 T
Q
, it is possible to specify multiple sampling of the bus
Q
Q
. The PIC18FXX8 defines this time to be 2 T
to 8 T
Q
Q
to 8 T
PROPAGATION SEGMENT
PHASE BUFFER SEGMENTS
SAMPLE POINT
INFORMATION PROCESSING TIME
by setting the PRSEG2:PRSEG0 bits.
Q
, or it may be defined to be equal to the
Q
in duration. However, due to IPT
 2002 Microchip Technology Inc.
Q
to 8 T
Q
/2 between
Q
Q
long.
in dura-
Q
.