PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 185

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

18.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA register) also controls the
baud rate. In Synchronous mode, bit BRGH is ignored.
Table 18-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
EXAMPLE 18-1:
TABLE 18-1:
TABLE 18-2:
 2002 Microchip Technology Inc.
Desired Baud Rate
Solving for X:
Calculated Baud Rate
Error
Legend: X = value in SPBRG (0 to 255)
TXSTA
RCSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
Name
SYNC
0
1
USART Baud Rate Generator
(BRG)
Baud Rate Generator Register
CSRC
SPEN
Bit 7
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
CALCULATING BAUD RATE ERROR
Bit 6
TX9
RX9
X = ( (F
X = ((16000000 / 9600) / 64) - 1
X = [25.042] = 25
= F
= 16000000 / (64 (25 + 1))
= 9615
= (Calculated Baud Rate - Desired Baud Rate)
= (9615 - 9600) / 9600
= 0.16%
BRGH = 0 (Low Speed)
SREN
OSC
TXEN
Bit 5
OSC
/ (64 (X + 1))
OSC
/ Desired Baud Rate) / 64 ) - 1
Desired Baud Rate
, the nearest
SYNC
CREN
Bit 4
OSC
OSC
/(4(X+1))
/(64(X+1))
ADDEN
Preliminary
Bit 3
—
BRGH
FERR
Bit 2
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
18.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
OERR
TRMT
Bit 1
Baud Rate = F
NA
SAMPLING
F
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
OSC
OSC
TX9D
RX9D
Bit 0
/(16(X + 1)) equation can reduce the
= 16 MHz
BRGH = 1 (High Speed)
0000 -010
0000 000x
0000 0000
POR, BOR
PIC18FXX8
Value on
OSC
/(16(X+1))
DS41159B-page 183
0000 -010
0000 000x
0000 0000
Value on
RESETS
all other