PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 377

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PWM (ECCP Module) ...................................................... 132
Q
Q Clock ............................................................................ 126
R
RAM. See Data Memory.
RCALL .............................................................................. 307
RCON Register
RCSTA Register ............................................................... 181
Receiver Warning ............................................................. 235
Register File ....................................................................... 44
Register File Summary ....................................................... 49
Registers
2002 Microchip Technology Inc.
Associated Registers ............................................... 139
Direction Change in Full-Bridge Output Mode ......... 136
Enhanced CCP Auto-Shutdown ............................... 140
Full-Bridge Application Example .............................. 136
Full-Bridge Mode ...................................................... 135
Full-Bridge PWM Output Diagram ........................... 135
Half-Bridge Mode ..................................................... 134
Half-Bridge Output Diagram ..................................... 134
Half-Bridge Output Mode Applications Example ...... 134
Output Configurations .............................................. 132
Output Polarity Configuration ................................... 138
Output Relationships Diagram ................................. 133
Programmable Deadband Delay .............................. 138
PWM Direction Change at Near 100%
PWM Direction Change Diagram ............................. 137
Setup for PWM Operation ........................................ 139
Standard Mode ........................................................ 132
Start-up Considerations ........................................... 138
System Implementation ........................................... 138
Significance of Status bits vs.
SPEN bit .................................................................. 181
ADCON0 (A/D Control 0) ......................................... 237
ADCON1 (A/D Control 1) ......................................... 238
BRGCON1 (Baud Rate Control 1) ........................... 215
BRGCON2 (Baud Rate Control 2) ........................... 216
BRGCON3 (Baud Rate Control 3) ........................... 217
CANCON (CAN Control) .......................................... 199
CANSTAT (CAN Status) .......................................... 200
CCP1CON (CCP1 Control) ...................................... 121
CIOCON (CAN I/O Control) ..................................... 217
CMCON (Comparator Control) ................................ 245
COMSTAT (CAN Communication Status) ............... 203
CONFIG1H (Configuration 1 High) .......................... 262
CONFIG2H (Configuration 2 High) .......................... 263
CONFIG2L (Configuration 2 Low) ............................ 262
CONFIG4L (Configuration 4 Low) ............................ 263
CONFIG5H (Configuration 5 High) .......................... 264
CONFIG5L (Configuration 5 Low) ............................ 264
CONFIG6H (Configuration 6 High) .......................... 265
CONFIG6L (Configuration 6 Low) ............................ 265
CONFIG7H (Configuration 7 High) .......................... 266
CONFIG7L (Configuration 7 Low) ............................ 266
CVRCON (Comparator Voltage
Device ID Register 1 ................................................ 267
Device ID Register 2 ................................................ 267
ECCP1CON (ECCP1 Control) ................................. 129
ECCP1DEL (PWM Delay) ........................................ 138
ECCPAS (Enhanced Capture/Compare/PWM
Duty Cycle Diagram ......................................... 137
Initialization Condition ........................................ 27
Reference Control) ........................................... 251
Auto-Shutdown Control) ................................... 140
Preliminary
EECON1 (EEPROM Control 1) ............................60, 67
INTCON (Interrupt Control) ........................................ 79
INTCON2 (Interrupt Control 2) ................................... 80
INTCON3 (Interrupt Control 3) ................................... 81
IPR1 (Peripheral Interrupt Priority 1) ......................... 88
IPR2 (Peripheral Interrupt Priority 2) ......................... 89
IPR3 (Peripheral Interrupt Priority 3) ......................... 90
IPR3 (Peripheral Interrupt Priority) .......................... 220
LVDCON (LVD Control) ........................................... 257
OSCCON (Oscillator Control) .................................... 20
PIE1 (Peripheral Interrupt Enable 1) .......................... 85
PIE2 (Peripheral Interrupt Enable 2) .......................... 86
PIE3 (Peripheral Interrupt Enable 3) .......................... 87
PIE3 (Peripheral Interrupt Enable) ........................... 219
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 82
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 83
PIR3 (Peripheral Interrupt Flag) ............................... 218
PIR3 (Peripheral Interrupt Request (Flag) 3) ............. 84
RCON (Reset Control) ..........................................58, 91
RCSTA (USART Receive Status) ............................ 182
RXB0CON (Receive Buffer 0 Control) ..................... 208
RXB1CON (Receive Buffer 1 Control) ..................... 209
RXBnDLC (Receive Buffer n
RXBnDm (Receive Buffer n Data
RXBnEIDH (Receive Buffer n Extended
RXBnEIDL (Receive Buffer n Extended
RXBnSIDH (Receive Buffer n Standard
RXBnSIDL (Receive Buffer n Standard
RXERRCNT (Receive Error Count) ......................... 212
RXFnEIDH (Receive Acceptance Filter n
RXFnEIDL (Receive Acceptance Filter n
RXFnSIDH (Receive Acceptance Filter n
RXFnSIDL (Receive Acceptance Filter n
RXMnEIDH (Receive Acceptance Mask n
RXMnEIDL (Receive Acceptance Mask n
RXMnSIDH (Receive Acceptance Mask n
RXMnSIDL (Receive Acceptance Mask n
SSPCON1 (MSSP Control 1) .................................. 143
SSPCON1 (MSSP Control 1) (I
SSPCON2 (MSSP Control 2) (I
SSPSTAT (MSSP Status) ........................................ 142
SSPSTAT (MSSP Status) (I
STATUS .................................................................... 57
STKPTR (Stack Pointer) ............................................ 39
T0CON (Timer0 Control) ......................................... 107
T1CON (Timer1 Control) ......................................... 111
T2CON (Timer2 Control) ......................................... 115
T3CON (Timer3 Control) ......................................... 117
TRISE (PORTE Direction/PSP Control) .................. 103
TXBnCON (Transmit Buffer n Control) .................... 204
Data Length Code) .......................................... 211
Field Byte m) ................................................... 211
Identifier,
High Byte) ........................................................ 210
Identifier, Low Byte) ......................................... 210
Identifier, High Byte) ........................................ 209
Identifier, Low Byte) ......................................... 210
Extended Identifier, High Byte) ........................ 213
Extended Identifier, Low Byte) ......................... 213
Standard Identifier Filter, High Byte) ............... 212
Standard Identifier Filter, Low Byte) ................ 212
Extended Identifier Mask, High Byte) .............. 214
Extended Identifier Mask, Low Byte) ............... 214
Standard Identifier Mask, High Byte) ............... 213
Standard Identifier Mask, Low Byte) ................ 214
PIC18FXX8
2
C Mode) ..................... 151
2
2
C Mode ................. 152
C Mode) ................ 153
DS41159B-page 375