PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 52

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX8
TABLE 4-2:
DS41159B-page 50
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
CCPR1H
CCPR1L
CCP1CON
ECCPR1H
ECCPR1L
ECCP1CON
ECCP1DEL
ECCPAS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
Legend:
Note
File Name
1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ’0’s.
2: Bit21 of the TBLPTRU allows access to the device configuration bits.
3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator
(1)
(1)
(1)
(1)
(1)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
(1)
modes.
(1)
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register1 High Byte
Capture/Compare/PWM Register1 Low Byte
Enhanced Capture/Compare/PWM Register1 High Byte
Enhanced Capture/Compare/PWM Register1 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
USART1 Baud Rate Generator
USART1 Receive Register
USART1 Transmit Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register2 (not a physical register)
EPWM1M1 EPWM1M0
ECCPASE
CVREN
EEPGD
ADCS1
EPDC7
C2OUT
WCOL
GCEN
ADFM
CSRC
SPEN
RD16
RD16
IRXIP
IRXIF
IRXIE
Bit 7
SMP
—
—
—
—
—
REGISTER FILE SUMMARY (CONTINUED)
TOUTPS3
ECCPAS2
ACKSTAT
T3ECCP1
CVROE
SSPOV
C1OUT
ADCS0
ADCS2
EPDC6
WAKIP
WAKIF
WAKIE
CFGS
CMIP
CMIF
CMIE
Bit 6
CKE
RX9
TX9
—
—
2
C Slave mode. SSP Baud Rate Reload Register in I
T1CKPS1
TOUTPS2
ECCPAS1
T3CKPS1
EDC1B1
SSPEN
ACKDT
EPDC5
DC1B1
ERRIP
ERRIF
ERRIE
CVRR
C2INV
SREN
CHS2
TXEN
Bit 5
D/A
—
—
—
—
—
TOUTPS1
ECCPAS0
T1CKPS0
T3CKPS0
EDC1B0
ACKEN
EPDC4
CVRSS
TXB2IP
TXB2IF
TXB2IE
DC1B0
C1INV
CREN
CHS1
SYNC
FREE
Bit 4
EEIP
EEIF
EEIE
CKP
Preliminary
—
P
T1OSCEN
ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000
TOUTPS0
CCP1M3
PSSAC1
T3CCP1
WRERR
SSPM3
ADDEN
TXB1IP
TXB1IF
TXB1IE
PCFG3
EPDC3
BCLIP
BCLIE
RCEN
BCLIF
CHS0
CVR3
Bit 3
CIS
—
S
GO/DONE
TMR2ON
CCP1M2
T1SYNC
PSSAC0
T3SYNC
SSPM2
PCFG2
EPDC2
TXB0IP
TXB0IF
TXB0IE
WREN
BRGH
LVDIP
LVDIE
CVR2
FERR
LVDIF
Bit 2
R/W
PEN
CM2
2
C Master mode.
T2CKPS1 T2CKPS0 -000 0000
TMR1CS
CCP1M1
TMR3CS
PSSBD1
RXB1IP
RXB1IE
TMR3IP ECCP1IP
TMR3IF ECCP1IF
TMR3IE ECCP1IE
SSPM1
PCFG1
EPDC1
RXB1IF
OERR
RSEN
TRMT
CVR1
Bit 1
CM1
WR
UA
—
 2002 Microchip Technology Inc.
TMR1ON 0-00 0000
TMR3ON 0000 0000
CCP1M0 --00 0000
PSSBD0 0000 0000
RXB0IP
RXB0IF
RXB0IE
SSPM0
PCFG0
EPDC0
ADON
CVR0
RX9D
TX9D
Bit 0
CM0
SEN
RD
BF
(1)
(1)
(1)
xxxx xxxx
xxxx xxxx
0000 0000
1111 1111
xxxx xxxx
0000 0000
0000 0000 31, 142, 151
0000 0000 31, 143, 152
0000 0000
xxxx xxxx
xxxx xxxx
0000 00-0
00-- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 -010
0000 000X
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx-0 x000 32, 60, 67
1111 1111
0000 0000
0000 0000
-1-1 1111
-0-0 0000
-0-0 0000
POR, BOR
Value on
Details on
31, 144
31, 150
31, 153
32, 239
32, 239
32, 237
32, 238
32, 122
32, 122
32, 121
32, 131
32, 131
32, 129
32, 138
32, 140
32, 251
32, 245
32, 183
32, 189
32, 187
32, 181
32, 182
31, 113
31, 113
31, 111
31, 116
31, 116
31, 115
32, 119
32, 119
32, 117
Page:
32, 59
32, 59
32, 59
32, 90
32, 84
32, 87
33, 89
33, 83
33, 86