PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 195

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

18.3.2
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register), or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
TABLE 18-9:
FIGURE 18-8:
 2002 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
Name
RC7/RX/DT pin
RC6/TX/CK pin
Note: Timing diagram demonstrates Sync Master mode with bit SREN = ’1’ and bit BRGH = ’0’.
(Interrupt)
CREN bit
Write to
bit SREN
SREN bit
RCIF bit
RXREG
Read
USART SYNCHRONOUS MASTER
RECEPTION
USART Receive Register
Baud Rate Generator Register
GIE/GIEH PEIE/GIEL TMR0IE
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
’0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit0
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit1
INT0IE
CREN
SYNC
Bit 4
TXIF
TXIE
TXIP
Preliminary
bit2
ADDEN
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
—
bit3
Steps to follow when setting up a Synchronous Master
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
Initialize the SPBRG register for the appropriate
baud rate (Section 18.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bit4
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
Bit 1
bit5
TMR1IE
TMR1IP
TMR1IF
RX9D
TX9D
Bit 0
RBIF
bit6
PIC18FXX8
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
bit7
DS41159B-page 193
Q1 Q2 Q3 Q4
0000 000u
0000 0000
0000 0000
0000 0000
0000 000x
0000 0000
0000 -010
0000 0000
Value on
RESETS
all other
’0’