PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 263

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

24.0
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
• OSC Selection
• RESET
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming
All PIC18FXX8 devices have a Watchdog Timer, which
is permanently enabled via the configuration bits or
software controlled. It runs off its own RC oscillator for
added reliability. There are two timers that offer neces-
sary delays on power-up. One is the Oscillator Start-up
Timer (OST), intended to keep the chip in RESET until
the crystal oscillator is stable. The other is the Power-
up Timer (PWRT), which provides a fixed delay on
power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
TABLE 24-1:
300001h
300002h
300003h
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
3FFFFEh
3FFFFFh
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
2002 Microchip Technology Inc.
Note 1: See Register 24-11 for DEVID1 values.
File Name
SPECIAL FEATURES OF THE
CPU
Shaded cells are unimplemented, read as ‘0’.
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
DEVID1
DEVID2
CONFIGURATION BITS AND DEVICE IDS
DEBUG
DEV10
WRTD
DEV2
Bit 7
CPD
—
—
—
—
—
—
—
EBTRB
WRTB
DEV1
DEV9
Bit 6
CPB
—
—
—
—
—
—
—
OSCSEN
WRTC
DEV0
DEV8
Bit 5
—
—
—
—
—
—
—
—
Preliminary
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
—
—
—
WDTPS2
BORV1
EBTR3
WRT3
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits is used to select various options.
24.1
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using Table Reads and
Table Writes.
Programming the configuration registers is done in a
manner similar to programming the FLASH memory.
The EECON1 register WR bit starts a self-timed write
to the configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointed to the
configuration register sets up the address and the data
for the configuration register write. Setting the WR bit
starts a long write to the configuration register. The con-
figuration registers are written a byte at a time. To write
or erase a configuration cell, a TBLWT instruction can
write a ‘1’ or a ‘0’ into the cell.
REV3
DEV6
Bit 3
CP3
—
—
—
—
—
Configuration Bits
WDTPS1
FOSC2
BORV0
EBTR2
WRT2
REV2
DEV5
Bit 2
CP2
LVP
—
—
—
WDTPS0
BOREN
FOSC1
EBTR1
WRT1
REV1
DEV4
Bit 1
CP1
—
—
—
—
PIC18FXX8
PWRTEN
STVREN
WDTEN
FOSC0
EBTR0
WRT0
REV0
DEV3
Bit 0
CP0
—
—
—
DS41159B-page 261
Unprogrammed
--1- -111
---- 1111
---- 1111
1--- -1-1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
0000 1000
Default/
Value
(1)