PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 167

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

17.4.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I
P bit is set or the bus is IDLE, with both the S and P bits
clear.
In Firmware Controlled Master mode, user code con-
ducts all I
STOP bit conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
FIGURE 17-16:
 2002 Microchip Technology Inc.
Assert a START condition on SDA and SCL.
Assert a Repeated START condition on SDA
and SCL.
Write to the SSPBUF register initiating transmis-
sion of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a STOP condition on SDA and SCL.
SDA
SCL
2
MASTER MODE
C bus operations based on START and
2
C port to receive data.
MSSP BLOCK DIAGRAM (I
2
C bus may be taken when the
SDA in
Bus Collision
SCL in
Read
MSb
START bit, STOP bit,
Write Collision Detect
end of XMIT/RCV
START bit Detect
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
SSPBUF
Generate
SSPSR
Preliminary
2
C MASTER MODE)
LSb
Write
The following events will cause SSP interrupt flag bit,
SSPIF, to be set (SSP interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated START
Clock
Data Bus
Shift
Note:
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
The MSSP Module, when configured in I
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
PIC18FXX8
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
DS41159B-page 165
2
C