AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 174

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.8.3
22.8.3.1
22.8.3.2
Figure 22-12. Write Cycle
174
AT91SAM9R64/RL64 Preliminary
Write Waveforms
NWE Waveforms
NCS Waveforms
NBS0, NBS1,
NBS2, NBS3,
A0, A1
A
[25:2]
MCK
NWE
NCS
The write protocol is similar to the read protocol. It is depicted in
starts with the address setting on the memory address bus.
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.
The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined:
1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before
2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE
3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after
1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before
2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and
3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the
NCS_WR_SETUP
the NWE falling edge;
rising edge;
the NWE rising edge.
the NCS falling edge.
NCS rising edge;
NCS rising edge.
NWE_SETUP
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NWE_HOLD
NCS_WR_HOLD
Figure
22-12. The write cycle
6289C–ATARM–28-May-09