AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 578

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

37.3.4.3
6289C–ATARM–28-May-09
Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4)
Note:
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in mem-
3. Write the channel configuration information into the DMAC_CFGx register for channel
4. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory
5. Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory
6. Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all
7. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register
8. If source picture-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), pro-
9. If destination picture-in-picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), pro-
10. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in
12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
13. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n
14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
15. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to sys-
ory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx
registers location of the buffer descriptor for each LLI in memory (see
page
h. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
x.
(except the last) are set as shown in Row 4 of
LLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in
Row 1 of
list items.
(except the last) are non-zero and point to the base address of the next Linked List
Item.
LLI entries in memory point to the start source/destination buffer address preceding
that LLI fetch.
locations of all LLI entries in memory are cleared.
gram the DMAC_SPIPx register for channel x.
gram the DMAC_DPIPx register for channel x.
ing the status register: DMAC_EBCISR.
Table 37-1 on page
Linked List item.
is the channel number. The transfer is performed.
tem memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF)
where it was originally fetched, that is, the location of the DMAC_CTRLAx register of
The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the
DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx chan-
nel registers from the DMAC_DSCRx(0).
579) for channel x. For example, in the register, you can program the following:
Table
37-1.
575.
Figure 37-4 on page 574
AT91SAM9R64/RL64 Preliminary
Table 37-1 on page
shows a Linked List example with two
575. The
Figure 37-5 on
578