AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 829

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

43.5.5
43.6
43.6.1
6289C–ATARM–28-May-09
Touch Screen
Sample and Hold Time
Resistive Touch Screen Principles
Mode
conversion of the sequence.
The field STARTUP can define a Startup Time between 8 and 1024 ADC Clock cycles by steps
of 8.
The user must assure that ADC Startup Time given in the section “Electrical Characteristics” is
covered by this wait time.
In the same way, a minimal Sample and Hold Time is necessary for the TSADCC to guarantee
the best converted final value between selection of two channels. This time depends on the input
impedance of the analog input, but also on the output impedance of the driver providing the sig-
nal to the analog input, as there is no input buffer amplifier.
The Sample and Hold time has to be programmed through the bitfields SHTIM in the
Mode Register”
The field SHTIM defines the number of ADC Clock cycles for an analog input, while the field
TSSHTIM defines the number of ADC Clock cycles for a Touch Screen input.
These both fields can define a Sample and Hold time between 1 and 16 ADC Clock cycles.
The field TSSHTIM defines also the time the power switches of the Touch Screen are closed
when the TSADCC performs a conversion for the Touch Screen.
A resistive touch screen is based on two resistive films, each one being fitted with a pair of elec-
trodes, placed at the top and bottom on one film, and on the right and left on the other. Between
the two, there is a layer that acts as an insulator, but also enables contact when you press the
screen. This is illustrated in
Register”, which defines how many ADC Clock cycles to wait before performing the first
and TSSHTIM in the
Figure
AT91SAM9R64/RL64 Preliminary
43-2.
“TSADCC Touch Screen
Register”.
“TSADCC
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