AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 720

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

40.7
Table 40-4.
720
0x100- 0x124
0x18-0x1C
0x60-0xFB
0x0-0x4
Offset
0x2C
0x3C
0x4C
0x5C
0x10
0x14
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
0x50
0x54
0x58
0xC
0x8
AC’97 Controller (AC97C) User Interface
AT91SAM9R64/RL64 Preliminary
Register Mapping
Reserved
Mode Register
Reserved
Input Channel Assignment Register
Output Channel Assignment Register
Reserved
Channel A Receive Holding Register
Channel A Transmit Holding Register
Channel A Status Register
Channel A Mode Register
Channel B Receive Holding Register
Channel B Transmit Holding Register
Channel B Status Register
Channel B Mode Register
Codec Receive Holding Register
Codec Transmit Holding Register
Codec Status Register
Codec Mode Register
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Reserved
Reserved for Peripheral Data Controller (PDC),
registers related to Channel A transfers
Register
AC97C_CARNCR,
AC97C_CARNPR,
AC97C_CAPTCR,
AC97C_CATNPR,
AC97C_CATNCR,
AC97C_CAPTSR
AC’97C_COTHR
AC97C_CARPR,
AC97C_CARCR,
AC97C_CORHR
AC97C_CATCR,
AC97C_CARHR
AC97C_CBRHR
AC97C_CBTHR
AC97C_CATPR,
AC97C_CATHR
Register Name
AC’97C_COMR
AC’97C_COSR
AC97C_CAMR
AC97C_CBMR
AC97C_CASR
AC97C_CBSR
AC97C_OCA
AC97C_IMR
AC97C_IDR
AC97C_MR
AC97C_ICA
AC97C_IER
AC97C_SR
–
–
–
–
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Access
Read
Write
Read
Read
Write
Read
Read
Write
Read
Read
Write
Write
Read
–
–
–
–
–
6289C–ATARM–28-May-09
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
–
–
–
–
–
–
–
–
–
–