AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 20

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.3
7.4
Table 7-3.
7.5
20
0
1
2
3
4
5
Matrix Slaves
Master to Slave Access
Peripheral DMA Controller (PDC)
AT91SAM9R64/RL64 Preliminary
LCD Controller User Interface
AT91SAM9R64/RL64 Master to Slave Access
UDP High Speed RAM
External Bus Interface
Peripheral Bridge
Masters
Slaves
Internal SRAM
Internal ROM
Table 7-1.
The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own
arbiter, allowing a different arbitration per slave.
Table 7-2.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the USB Device High speed DMA to the Internal Peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Master 3
Master 4
Master 5
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
• Acting as one AHB Bus Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
• Next Pointer support, prevents strong real-time constraints on buffer management.
of the processor.
List of Bus Matrix Masters
List of Bus Matrix Slaves
Controller
DMA
Peripheral DMA Controller
ARM926
ARM926 Data
Internal ROM
Internal SRAM
LCD Controller User Interface
UDP High Speed RAM
External Bus Interface (EBI)
Peripheral Bridge
0
X
X
X
X
-
-
™
Device DMA
Instruction
USB HS
X
X
X
X
1
-
-
Controller
DMA
LCD
X
X
X
2
-
-
Peripheral
DMA
X
X
X
3
-
-
-
Instruction
ARM926
6289C–ATARM–28-May-09
X
X
X
X
X
4
-
ARM926
Data
X
5
X
X
X
X
-