AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 57

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.3.9
12.3.10
6289C–ATARM–28-May-09
New ARM Instruction Set
Thumb Instruction Set Overview
.
Table 12-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Table 5 shows the Thumb instruction set.
Table 12-4.
Mnemonic
Mnemonic
MOV
ADD
SUB
CMP
TST
AND
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
SMULWy
SMLAWy
SMLAxy
SMULxy
QDADD
QDSUB
SMLAL
BLX
QADD
QSUB
BXJ
(1)
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
Operation
Move
Add
Subtract
Compare
Test
Logical AND
New ARM Instruction Mnemonic List
Thumb Instruction Mnemonic List
Operation
Branch and exchange to
Java
Branch, Link and exchange
Signed Multiply Accumulate
16 * 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate
32 * 16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with
double
AT91SAM9R64/RL64 Preliminary
Table 12-4
Mnemonic
MVN
ADC
SBC
CMN
NEG
BIC
Mnemonic
MRRC
MCRR
MCR2
CDP2
BKPT
STRD
LDRD
STC2
LDC2
PLD
CLZ
gives the Thumb instruction mnemonic list.
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Bit Clear
Operation
Move double from
coprocessor
Alternative move of ARM reg
to coprocessor
Move double to coprocessor
Alternative Coprocessor
Data Processing
Breakpoint
Soft Preload, Memory
prepare to load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Coprocessor
Count Leading Zeroes
Alternative Load to
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