AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 716

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

40.6.3
716
31
31
31
31
31
31
To Receive Word transfers
To Receive Halfword Transfers
To Receive 10-bit Samples
AT91SAM9R64/RL64 Preliminary
Variable Sample Rate
Byte0[7:0]
–
–
–
–
–
Data received on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}.
Word stored in AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR)
(Received Data)
Data is read from AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when
Channel x data size is greater than 16 bits and when big-endian mode is enabled (data written to
memory).
Data received on appropriate slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}.
Halfword stored in AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR)
(Received Data).
Data is read from AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when
data size is equal to 16 bits and when big-endian mode is enabled.
Data received on appropriate slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}.Halfword stored
in AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR) (Received Data)
Data read from AC’97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when
data size is equal to 10 bits and when big-endian mode is enabled.
The problem of variable sample rate can be summarized by a simple example. When passing a
44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441
of them must contain valid sample data. The new AC’97 standard approach calls for the addition
of “on-demand” slot request flags. The AC‘97 Codec examines its sample rate control register,
the state of its FIFOs, and the incoming SDATA_OUT tag bits (slot 0) of each output frame and
then determines which SLOTREQ bits to set active (low). These bits are passed from the AC97
24
24
24
24
24
24
23
23
23
23
23
23
–
Byte1[7:0]
20
.
–
–
–
–
19
Byte2[3:0]
16
16
16
16
16
16
15
15
15
15
15
{0x0, Byte2[3:0]}
Byte0[7:0]
Byte1[7:0]
Byte1[7:0]
Byte0[7:0]
–
15
10
Byte1
9
[1:0]
8
8
8
8
8
8
7
7
7
7
7
7
0x00
Byte0[7:0]
Byte0[7:0]
Byte1[7:0]
6289C–ATARM–28-May-09
Byte0[7:0]
0x00
3
Byte1
1
[1:0]
0
0
0
0
0
0