AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 708
AT91SAM9RL64-CU
Manufacturer Part Number
AT91SAM9RL64-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9RL64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
118
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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40.5
40.5.1
40.5.2
40.5.3
708
Product Dependencies
AT91SAM9R64/RL64 Preliminary
I/O Lines
Power Management
Interrupt
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the AC‘97 Controller receiver, the PIO controller must be configured in order for the
AC97C receiver I/O lines to be in AC‘97 Controller peripheral mode.
Before using the AC‘97 Controller transmitter, the PIO controller must be configured in order for
the AC97C transmitter I/O lines to be in AC‘97 Controller peripheral mode.
The AC‘97 Controller is not continuously clocked. Its interface may be clocked through the
Power Management Controller (PMC), therefore the programmer must first configure the PMC
to enable the AC’97 Controller clock.
The AC’97 Controller has two clock domains. The first one is supplied by PMC and is equal to
MCK. The second one is AC97CK which is sent by the AC97 Codec (Bit clock).
Signals that cross the two clock domains are re-synchronized. MCK clock frequency must be
higher than the AC97CK (Bit Clock) clock frequency.
The AC’97 Controller interface has an interrupt line connected to the Advanced Interrupt Con-
troller (AIC). Handling interrupts requires programming the AIC before configuring the AC97C.
All AC’97 Controller interrupts can be enabled/disabled by writing to the AC’97 Controller Inter-
rupt Enable/Disable Registers. Each pending and unmasked AC’97 Controller interrupt will
assert the interrupt line. The AC’97 Controller interrupt service routine can get the interrupt
source in two steps:
• Reading and ANDing AC’97 Controller Interrupt Mask Register (AC97C_IMR) and AC’97
• Reading AC’97 Controller Channel x Status Register (AC97C_CxSR).
Controller Status Register (AC97C_SR).
6289C–ATARM–28-May-09
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