AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 796

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

This bit is set when flushing unsent banks at the end of a microframe.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
• NAK_OUT: NAK OUT
This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
• CURRENT_BANK/CONTROL_DIR: Current Bank/Control Direction
These bits are set by hardware to indicate the number of the current bank.
Note: the current bank is updated each time the user:
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
0 = a Control Write is requested by the Host.
1 = a Control Read is requested by the Host.
Note1: This bit corresponds with the 7th bit of the bmRequestType (Byte 0 of the Setup Data).
Note2: This bit is updated after receiving new setup data.
• BUSY_BANK_STA: Busy Bank Number
These bits are set by hardware to indicate the number of busy banks.
• BYTE_COUNT: UDPHS Byte Count
Byte count of a received data packet.
This field is incremented after each write into the endpoint (to prepare an IN transfer).
This field is decremented after each reading into the endpoint (OUT transfer).
796
00
01
10
11
00
01
10
11
IN endpoint: it indicates the number of busy banks filled by the user, ready for IN transfer.
OUT endpoint: it indicates the number of busy banks filled by OUT transaction from the Host.
– ERR_FLUSH: (for High Bandwidth Isochronous IN endpoints)
– Current Bank: (all endpoints except Control endpoint)
– Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.
– Clears the received OUT data bit to access the next bank.
– Control Direction: (for Control endpoint only)
Bank 0 (or single bank)
Bank 1
Bank 2
Invalid
All banks are free
1 busy bank
2 busy banks
3 busy banks
AT91SAM9R64/RL64 Preliminary
6289C–ATARM–28-May-09