AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 718

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 40-7. AC’97 Power-Down/Up Sequence
40.6.4.3
718
Cold AC’97 Reset
Warm AC’97 Reset
AT91SAM9R64/RL64 Preliminary
AC97 Codec Reset
AC97CK
AC97RX
AC97FS
AC97TX
This feature is implemented in AC97 modem codecs that need to report events such as Caller-
ID and wake-up on ring.
The AC97 Codec can drive AC97RX signal from low to high level and holding it high until the
controller issues either a cold or a worm reset. The AC97RX rising edge is asynchronously
(regarding AC97FS) detected by the AC’97 Controller. If WKUP bit is enabled in AC97C_IMR
register, an interrupt is triggered that wakes up the AC‘97 Controller which should then immedi-
ately issue a cold or a warm reset.
If the processor needs to be awakened by an external event, the AC97RX signal must be exter-
nally connected to the WAKEUP entry of the system controller.
There are three ways to reset an AC97 Codec.
A cold reset is generated by asserting the RESET signal low for the minimum specified time
(depending on the AC97 Codec) and then by de-asserting RESET high. AC97CK and AC97FS
is reactivated and all AC97 Codec registers are set to their default power-on values. Transfers
on AC-link can resume.
The RESET signal will be controlled via a PIO line. This is how an application should perform a
cold reset:
AC97CK, the clock provided by AC97 Codec, is detected by the controller.
A warm reset reactivates the AC-link without altering AC97 Codec registers. A warm reset is sig-
naled by driving AC97FX signal high for a minimum of 1us in the absence of AC97CK. In the
absence of AC97CK, AC97FX is treated as an asynchronous (regarding AC97FX) input used to
signal a warm reset to AC97 Codec.
This is the right way to perform a warm reset:
• Clear and set ENA flag in the AC97C_MR register to reset the AC’97 Controller
• Clear PIO line output controlling the AC’97 RESET signal
• Wait for the minimum specified time
• Set PIO line output controlling the AC’97 RESET signal
• Set WRST in the AC97C_MR register.
TAG
TAG
Power Down Frame
Write to
Write to
0x26
0x26
Data
Data
PR4
PR4
Sleep State
Wake Event
Warm Reset
TAG
TAG
New Audio Frame
Slot1
Slot1
Slot2
Slot2
6289C–ATARM–28-May-09