AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 63

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.6.1
12.6.2
12.6.2.1
6289C–ATARM–28-May-09
Instruction Cache (ICache)
Data Cache (DCache) and Write Buffer
DCache
A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly
known as wrapping. This feature enables the caches to perform critical word first cache refilling.
This means that when a request for a word causes a read-miss, the cache performs an AHB
access. Instead of loading the whole line (eight words), the cache loads the critical word first, so
the processor can reach it quickly, and then the remaining words, no matter where the word is
located in the line.
The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7
(cache operations) and CP15 register 9 (cache lockdown).
The ICache caches fetched instructions to be executed by the processor. The ICache can be
enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit.
When the MMU is enabled, all instruction fetches are subject to translation and permission
checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are
made and the physical address is flat-mapped to the modified virtual address. With the MVA use
disabled, context switching incurs ICache cleaning and/or invalidating.
When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see
Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM, ref. DDI0198B).
On reset, the ICache entries are invalidated and the ICache is disabled. For best performance,
ICache should be enabled as soon as possible after reset.
ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory band-
width and latency on data access performance. The operations of DCache and write buffer are
closely connected.
The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission
and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data
accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are
noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All
addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating
every time a context switch occurs.
The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and
uses it when writing modified lines back to external memory. This means that the MMU is not
involved in write-back operations.
Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other
one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the
cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide
whether all, half or none is written back to memory.
DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see
Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B).
The DCache supports write-through and write-back cache operations, selected by memory
region using the C and B bits in the MMU translation tables.
AT91SAM9R64/RL64 Preliminary
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