MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 139
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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5.5.3.2
The command sequence diagram in
represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system
sends to the debug module; the bottom half indicates the debug module’s response to the previous
development system commands. Command and result transactions overlap to minimize latency.
The sequence is as follows:
Freescale Semiconductor
•
•
In cycle 1, the development system command is issued (
responds with either the low-order results of the previous command or a command complete status
of the previous command, if no results are required.
In cycle 2, the development system supplies the high-order 16 address bits. The debug module
returns a not-ready response unless the received command is decoded as unimplemented, which is
indicated by the illegal command encoding. If this occurs, the development system should
retransmit the command.
COMMANDS TRANSMITTED TO THE DEBUG MODULE
RESPONSES FROM THE DEBUG MODULE
READ (LONG)
???
Command Sequence Diagrams
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
RESULTS FROM PREVIOUS COMMAND
COMMAND CODE TRANSMITTED DURING THIS CYCLE
MCF5272 ColdFire
SEQUENCE TAKEN IF
ILLEGAL COMMAND
IS RECEIVED BY DEBUG MODULE
"NOT READY"
MS ADDR
"ILLEGAL"
XXX
Figure 5-16. Command Sequence Diagram
HIGH-ORDER 16 BITS OF MEMORY ADDRESS
Figure 5-16
®
Integrated Microprocessor User’s Manual, Rev. 3
DATA UNUSED FROM
THIS TRANSFER
"NOT READY"
"NOT READY"
NEXT CMD
LS ADDR
LOW-ORDER 16 BITS OF MEMORY ADDRESS
shows serial bus traffic for commands. Each bubble
NOTE
LOCATION
MEMORY
READ
NONSERIAL-RELATED ACTIVITY
READ
HIGH- AND LOW-ORDER
16 BITS OF RESULT
in this example). The debug module
ERROR OCCURS ON
SEQUENCE TAKEN IF
OPERATION HAS NOT
COMPLETED
SEQUENCE TAKEN IF BUS
MEMORY ACCESS
"NOT READY"
MS RESULT
XXX
XXX
XXXXX
BERR
XXX
"NOT READY"
COMMAND
NEXT CMD
LS RESULT
NEXT CMD
NEXT
CODE
Debug Support
5-21
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