MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 327

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

13.5.19 D-Channel Status Register (PDCSR)
All bits in this register are read only and are cleared on hardware or software reset. The register is also
cleared after a read operation.
The PDCSR register contains the D-channel status bits for all four ports on the MCF5272.
Freescale Semiconductor
Bits
7–6
5
4
3
2
1
0
Name
DG1
DG0
DC3
DC2
DC1
DC0
—
Reset
Field
Addr
R/W
Reserved, should be cleared.
D-channel grant, port 1.
0 Default reset value.
1 In IDL mode, indicates the status of DGRANT. When the external DGNT has a logic 1, the
D-channel grant, port 0. See DG1.
D-channel change, port 3.
0 Default reset value.
1 Indicates that a value other than 0xFF (all ones) exists the D-channel receive register.
D-channel change, port 2. See DC3.
D-channel change, port 1. See DC3.
D-channel change, port 0. See DC3.
MCF5272 ColdFire
corresponding DG1/DG0 bit is set. In GCI mode, DG1 and DG0 reflects the inverted value of the
SCIT bit. The significance of this bit is the same in IDL or GCI mode, that is, in IDL mode when the
DG bit is set, the D channel is granted. In GCI mode when the DG bit is set, this corresponds to the
GO condition. In both cases the D channel is granted and communication may commence.
7
Figure 13-31. D-Channel Status Register (PDCSR)
—
Table 13-14. PDCSR Field Descriptions
6
®
Integrated Microprocessor User’s Manual, Rev. 3
DG1
5
MBAR + 0x383
DG0
0000_0000
Read Only
4
Description
DC3
3
DC2
2
Physical Layer Interface Controller (PLIC)
DC1
1
DC0
0
13-31