MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 78

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

ColdFire Core
2.4
The following sections describe data organization within the data, address, and control registers.
2.4.1
Figure 2-7
word operands occupy the lower 8- and 16-bit portions of integer data registers, respectively. Longword
operands occupy the entire 32 bits of integer data registers. A data register that is either a source or
destination operand only uses or changes the appropriate lower 8 or 16 bits in byte or word operations,
respectively. The remaining high-order portion does not change. The least significant bit (lsb) of all integer
sizes is zero, the most-significant bit (msb) of a longword integer is 31, the msb of a word integer is 15,
and the msb of a byte integer is 7.
The instruction set encodings do not allow the use of address registers for byte-sized operands. When an
address register is a source operand, either the low-order word or the entire longword operand is used,
depending on the operation size. Word-length source operands are sign-extended to 32 bits and then used
in the operation with an address register destination. When an address register is a destination, the entire
register is affected, regardless of the operation size.
The size of control registers varies according to function. Some have undefined bits reserved for future
definition by Freescale. Those particular bits read as zeros and must be written as zeros for future
compatibility.
All operations to the SR and CCR are word-size operations. For all CCR operations, the upper byte is read
as all zeros and is ignored when written, regardless of privilege mode.
2-10
Organization of Data in Registers
shows the integer format for data registers. Each integer data register is 32 bits wide. Byte and
msb
msb
Organization of Integer Data Formats in Registers
31
31
31
31
31
31
Figure 2-8. Organization of Integer Data Formats in Address Registers
30
30
Not used
MCF5272 ColdFire
Not used
Figure 2-7. Organization of Integer Data Formats in Data Registers
Sign-Extended
16
Longword
®
Integrated Microprocessor User’s Manual, Rev. 3
msb
Full 32-Bit Address Operand
15
8
msb Low order byte
14
7
Lower order word
16
Figure 2-8
6
15
1
1
1
1
shows integer formats for address registers.
16-Bit Address Operand
lsb
lsb
lsb
lsb
0
0
0
0
Bit (0 ð bit number ð 31)
Byte (8 bits)
Word (16 bits)
Longword (32 bits)
Freescale Semiconductor
0
0