MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 321
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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13.5.13 GCI Monitor Channel Transmit Registers (P0GMT–P3GMT)
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnGMT registers are 16 bit register containing the control and monitor channel bits to be transmitted
for each of the four ports on the MCF5272.
A byte of monitor channel data to be transmitted on a certain port is put into an associated register using
the format shown in
successfully transmitted.
Freescale Semiconductor
15–10
Bits
7–0
9
8
Reset
Field
Addr
R/W
Name
—
R
M
L
15
Reserved, should be cleared.
Last.
0 Default reset value
1 Set by the CPU. Indicates to the monitor channel controller to transmit the end of message signal on the
Ready.
0 Default reset value.
1 Set by the CPU. Indicate to the monitor channel controller that a byte of data is ready for transmission.
Monitor channel data byte. Written by the CPU when a byte is ready for transmission.
Figure 13-25. GCI Monitor Channel Transmit Registers (P0GMT–P3GMT)
E bit. Both PnGMT[L] and PnGMT[R] must be set for the monitor channel controller to send the end of
message signal. PnGMT[M7:0] are ignored and 0xFF is sent with the end of message condition
necessitating sending the monitor channel information using PnGMT[R] to control the monitor channel
transmitter, followed at the end of the frame by setting PnGMT[L] and PnGMT[R]. The L bit is automatically
cleared by the GCI controller.
Automatically cleared by the GCI controller when it generates a transmit acknowledge (ACK bit in PGMTS
register) or when the L bit is reset.
Figure
MCF5272 ColdFire
MBAR + 0x368 (P0GMT); 0x36A (P1GMT); 0x36C (P2GMT); 0x36E (P3GMT)
—
13-25. A maskable interrupt is generated when this byte of data has been
Table 13-8. P0GMT–P3GMT Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
10
0000_0000_0000_0000
L
9
Read/Write
R
8
Description
7
Physical Layer Interface Controller (PLIC)
M
0
13-25
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