MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 254
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Ethernet Module
11-36
Offset
Offset
10–9
Bits
+ 2
+ 4
15
14
13
12
11
8
7
6
5
4
3
2
1
0
Rx Buffer
Length
Pointer
Name
Data
RO1
RO2
MC
NO
CR
BC
LG
SH
OV
TR
W
—
M
E
L
Anytime the software driver sets an E bit in a receive descriptor, the driver
should immediately write to RDAR.
Empty. Written by the FEC (= 0) and user (= 1).
0 The data buffer associated with this BD has been filled with received data, or data reception has been
aborted due to an error condition. The status and length fields have been updated as required.
1 The data buffer associated with this BD is empty, or reception is currently in progress.
Receive software ownership. This field is reserved for use by software. This read/write bit is not modified
by hardware, nor does its value affect hardware.
Wrap. Written by the user.
0 =The next buffer descriptor is found in the consecutive location.
1 =The next buffer descriptor is found at the location defined in ERDSR.
Receive software ownership. Reserved for use by software. This read/write bit is not modified by
hardware, nor does its value affect hardware.
Last in frame. Written by the FEC.
0 =The buffer is not the last in a frame.
1 =The buffer is the last in a frame.
Reserved, should be cleared.
Miss. Written by the FEC. This bit is set by the FEC for frames that were accepted in promiscuous mode,
but were flagged as a miss by the internal address recognition. Thus, while in promiscuous mode, the
user can use the M-bit to quickly determine whether the frame was destined to this station. Valid only if
the L-bit and the PROM bit are set.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
Broadcast. Written by the FEC. Will be set if DA is broadcast. (FF-FF-FF-FF-FF-FF)
Mulitcast. Written by the FEC. Is set if DA is multicast and not BC.
Rx frame length violation. Written by the FEC. A frame length greater than MAX_FL was recognized.
Frames exceeding 2047 bytes are truncated to prevent wrapping hardware length counters. Valid only if
the L-bit is set.
Rx non-octet-aligned frame. Written by the FEC. A frame that contained a number of bits not divisible by
8 was received, and the CRC check that occurred at the preceding byte boundary generated an error.
Valid only if the L-bit is set. If this bit is set, the CR bit is not set.
Short frame. Written by the FEC. A frame length that was less than the minimum defined for this channel
was recognized. The FEC does not support SH and this bit is always cleared.
Rx CRC error. Written by the FEC. Contains a CRC error and is an integral number of octets in length.
Valid only if the L-bit is set.
Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If this bit is set,
the other status bits, M, LG, NO, SH, CR, and CL, lose their normal meaning and are zero. Valid only if
the L-bit is set.
Truncated receive frame. Written by the FEC. Set if the receive frame is truncated. Frames greater than
or equal to 2048 bytes are truncated.
Written by the FEC. Data length is the number of octets written by the FEC into this BD’s data buffer if L
= 0 (the value is equal to EMRBR), or the length of the frame including CRC if L = 1. It is written by the
FEC once as the BD is closed.
Written by the user. The receive buffer pointer, which always points to the first location of the associated
data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC.
MCF5272 ColdFire
Table 11-34. RxBD Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
Description
Freescale Semiconductor
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