MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 323
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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13.5.15 GCI Monitor Channel Transmit Status Register (PGMTS)
All bits in this register are read only and are cleared on hardware or software reset.
The PGMTS register contains the monitor channel status bits for each of the four transmit ports on the
MCF5272.
Freescale Semiconductor
Bits
7
6
5
4
3
2
1
0
Name
ACK3 Acknowledge, port 3.
ACK2 Acknowledge, port 2. See ACK3.
ACK1 Acknowledge, port 1. See ACK3.
ACK0 Acknowledge, port 0. See ACK3.
AB3
AB2
AB1
AB0
0 Default reset value.
1 Indicates to the CPU that the GCI controller has transmitted the previous monitor channel information.
Abort, port 3.
0 Default reset value.
1 Indicates to the CPU that the GCI controller has aborted the current message. This bit is automatically
Abort, port 2. See AB3.
Abort, port 1. See AB3.
Abort, port 0. See AB3.
Automatically cleared by the CPU reading the register. The clearing of this bit by reading this register also
clears the aperiodic GMT interrupt.
cleared by the CPU reading the register. When the GCI controller sets this bit, it also clears the AR bit in the
PGMTA register, the ACK bit in the GMTS register, and the L and R bits in the PnGMT register.
Figure 13-27. GCI Monitor Channel Transmit Status Register (PGMTS)
Reset
Field ACK3
Addr
R/W
MCF5272 ColdFire
7
Table 13-10. PGMTS Field Descriptions
ACK2
6
®
Integrated Microprocessor User’s Manual, Rev. 3
ACK1
5
ACK0
MBAR + 0x371
0000_0000
Read Only
4
Description
AB3
3
AB2
2
Physical Layer Interface Controller (PLIC)
AB1
1
AB0
0
13-27
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