MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 350
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Serial Peripheral Interface (QSPI) Module
14.5.3
Table 14-5
14-12
Address
Reset
11–8
Field
R/W
Bits
7–4
3–0
15
14
13
12
HALT WREN WRTO CSIV
gives QWR field descriptions.
15
NEWQP
ENDQP
CPTQP
QSPI Wrap Register (QWR)
WREN
WRTO
Name
HALT
CSIV
14
QSPI_CS inactive level.
Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once it has
completed execution of the current command.
Wraparound enable. Enables wraparound mode.
0 Execution stops after executing the command pointed to by QWR[ENDQP].
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed
Wraparound location. Determines where the QSPI wraps to in wraparound mode.
0 Wrap to RAM entry zero.
1 Wrap to RAM entry pointed to by QWR[NEWQP].
0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM
1 QSPI chip select outputs return to one when not driven from the value in the current command RAM
End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.
Completed queue entry pointer. Points to the RAM entry that contains the last command to have been
completed. This field is read only.
Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a
transfer.
MCF5272 ColdFire
to by QWR[NEWQP] and continue execution.
entry during a transfer (that is, inactive state is 0, chip selects are active high).
entry during a transfer (that is, inactive state is 1, chip selects are active low).
13
12
Figure 14-7. QSPI Wrap Register (QWR)
Table 14-5. QWR Field Descriptions
11
®
Integrated Microprocessor User’s Manual, Rev. 3
ENDQP
0000_0000_0000_0000
MBAR + 0x00A8
R/W
8
Description
7
–
4
Freescale Semiconductor
3
NEWQP
0
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